ADS127L21: Functional Safety AFE

Hallo Theo,

thanks a lot for your interest in our ADS127L21 for your functional safety PLC AI module design.

Without performing an actual FMEDA it is a little hard for me to determine what additional measures might be required to meet the metrics for SIL 2. Following just some thoughts:

• Communication faults can be detected using the SPI CRC.
• In addition you can detected a couple of device or communication faults when SDO is permanently low or high. I usually call this measure "host loss of communication detection". This can for example happen when the CSn pin cannot be drive low anymore or when the device went through an unintended reset, etc.
• Bit flips in the register map can be detected using the register map CRCs.
• Faults in the clock tree can be detected by monitoring the DRDYn output with a window watchdog. The conversions, and thus the DRDYn indication, are directly proportional to the clock frequency.
• Offset errors in the ADC can be detected by measuring the device offset. This can be done by leveraging the MUX[1:0] = 10b register setting.
• In order to detect gain errors or errors in the external VREF you would have to inject a separate test signal into the ADC in my opinion, which would require an external MUX.
  Faults in the external VREF could of course also be detected by measuring the VREF with an independent ADC, e.g. an ADC within the MCU.
• The test signal measurement might also be useful to detect faults in the Mux.
• In case you can create a variable test signal, e.g. using a DAC or PWM with RC filter, then you could use that also to check for any major stuck bits in the output codes.
• You might also want to monitor the supplies, but I assume you will do that anyway.

Let me know if that is any helpful.

I'll let Keith in our team comment on your input driver question. He is the main application engineer for the ADS127L21.

Viele Grüße,
Joachim Wuerker