Part Number: ADC3669EVM
Tool/software:
Hello,
I am experiencing an issue with the ADC3669EVM Devkit. Below, I will describe the problem.
The ADC3669EVM kit is running on the Agilex 7 platform - AGIB027R31B1E1VB. The device is connected to FMC B, and the sampling clock is set to 400 MHz.
The first issue I encountered is as follows: the device, purchased in December 2024, is labeled as REV. B on the silkscreen layer of the PCB. However, the documentation (schematics) available online corresponds to version C - REV. C.
The documentation states that component R125 is not soldered. This pin, pulled to GND, detects whether the module is connected to the FMC. In REV. B, such a designation does not exist. By tracing the pin from the FMC, I discovered that it corresponds to R188. Let’s say this problem has been resolved.
The next issue is more serious, namely data corruption on certain bits.
I configured the ADC test pattern to RAMP. On the FPGA side, I collect data on the rising and falling edges, and I observe the following effect: some bits are shifted.
The FPGA design is timing-consistent, so the issue likely isn't there. On the FPGA side, I tried shifting the CLK phase. The result was that the alignment improved for some bits but worsened for others.
I also attempted applying delays to individual lines from the FPGA. While this partially improved the situation, it didn't fully resolve the issue.
Could you assist with this problem?
