ADS9813EVM: Confusion regarding initialization sequence of ADS9813

Part Number: ADS9813EVM
Other Parts Discussed in Thread: ADS9813

Tool/software:

Hello,

We are using the ADS9813 EVM along with the Zynq 7045 FPGA. The ADS9813 is mounted on the FMC of the FPGA. We plan to use the ADS9813 in a 4-lane SDR data rate configuration.

We have built and verified the logic for this setup in Vivado through simulation, and now we intend to implement it on hardware. However, we encountered some confusion regarding the initialization sequence in the ADS9813 datasheet. Our queries are as follows:

  1. In Table 6-13 (Initialization Sequence), register 0x04 is mentioned with a value of 0x000B, but on page 39, it is stated to write 0x0003. Could you clarify the correct value?
  2. Registers 0x92 and 0xC5 belong to Bank 1, but Table 6-13 mentions selecting Bank 2 for these registers. Is this a mistake, or is there a specific reason for this?
  3. While observing fCLK in the ILA with the dCLK as the clock, we notice that fCLK is sometimes missing and does not appear as expected. Could you explain why this might be happening and provide suggestions to resolve it?
    Also if  Iam configuring sdr mode then fclk rise edge to rise edge  there should be 48 dclks . even if spi write is not done then for default configuration i.e ddr data rate with 4 data lanes it should be 24 dclks but iam not seeing fclk is repetiting for these dclks. it is repetitting for 65 dclks and 130 dclks sometimes and also missig for certain number of dclks.

  4. when we try initialize the registers 0x92 and 0XC5 by selecting bank 1 we are experiencing a power down situation where all data lanes and fclk are logic low.

It would be helpful if you could provide the correct final initialization sequence for the ADS9813 and clarify the behavior of fCLK.

Best regards

  • Hi CT,

    Thanks for your question. To better understand the use-case, could you please share what kind of an application you hope to use ADS9813 in?

    I am awaiting confirmation from the team regarding the initialization sequence, let me get back to you on Monday. Are applying power and a free-running SMPL_CLK while trying to write the init sequence? FCLK malfunctioning may be a symptom of the device not being initialized properly, so we should resolve that first.

    Best regards,

    Samiha

  • Hello,

    Any updates on the initialization sequence?

    I also wanted to let you know that we are setting the SPI clock polarity and phase to zero, as per the timing diagram. Could you confirm if we are on the right track?

    Best regards.

  • Hi CT,

    The confirmed sequence is as follows:

    1. 0x000B to 0x04 address
    2. 0x0002 to 0x03 address // select register bank 1
    3. 0x0002 to 0x92 address
    4. 0x0604 to 0xC5 address

    Yes, PHA and POL being 0 is correct for SPI.

    Could you please share your schematic of the ADC so I may confirm all connections are correct? Also could you please go through these debug steps:

    1. Measure AVDD_5V, IOVDD, VDD_1V8, and REFIO using a DMM to ensure all supplies are as expected.
    2. Apply SMPL_CLK
    3. Write the initialization sequence as I shared above. Could you please share oscilloscope screenshots (of all digital signals)?
    4. Were any supplies connected to the device previously that exceeded the max limits?

    Best regards,

    Samiha

  • Hello,

    We are using the evaluation board itself, and we have measured the voltages with the following results:

    • AVDD: 5V
    • IOVDD and VDD: 1.8V
    • REFIO: 4.1V

    After power-up, we are following the below sequence of register writes to initialize the ADS9813 and configure it for our use case:

    1. Write 0x0001 to register 0x00 (reset enabled).
    2. Write 0x0000 to register 0x00 (reset disabled).
    3. Write 0x0004 to register 0x00 (legacy SPI enabled).
    4. Write 0x000B to register 0x04 (INIT1 configuration).
    5. Write 0x0002 to register 0x03 (select bank 1).
    6. Write 0x0002 to register 0x92 (INIT2 configuration).
    7. Write 0x0604 to register 0xC5 (INIT3 configuration).
    8. Write 0x0100 to register 0xC1 (set SDR data rate).

    We are using an SPI clock of 5 MHz with CPOL = 0 and CPHA = 0.

    We are observing the data lanes (D0, D1, D2, D3) with respect to DCLK in the ILA and also monitoring FCLK in the ILA. The register initialization occurs based on our control logic.

    Here is what we observed:

    • Before initialization:

      • Data is present on the data lanes (D0, D1, D2, D3).
      • FCLK is captured in the ILA (not periodic but detectable).
    • After initialization:

      • All data lanes (D0, D1, D2, D3) and FCLK show zero in the ILA.
      • There is no data or activity observed.

    We are providing an 8 MHz clock through the FMC to SAMPL_CLKP. We are using the default jumper configuration (no changes made to jumper positions).

    Could you help us understand why we are not seeing any data or FCLK after initialization? Are we missing something in the initialization sequence? Have you encountered this issue?

    Your assistance is greatly appreciated, as we are currently stuck at this point.

    Best regards.

  • Hi CT,

    Thanks for sharing. We recently fully released the ADS9813 so the production silicon is a little different compared to the preproduction silicon. Perhaps your EVM has preproduction silicon, depending on when you ordered it. Could you share what the marking on your ADS9813 device is? Is it ADS9813 or PADS9813? If it is PADS9813, it will be best to order a production device and replace the DUT on the EVM, as this may be causing the initialization sequence issues. The sequence in the datasheet is meant for production silicon. 

    Productiom silicon of ADS9813: https://www.ti.com/product/ADS9813/part-details/ADS9813RSHR

    Best regards,

    Samiha

  • Hello Samiha,

    Thanks for your support. We have resolved the issue by creating a new project. We suspect a mismatch between the SDK and RTL, but we're not entirely sure. Now, we are able to perform initialization successfully. We tested with a custom pattern, which worked, and also verified it with an input signal.

    We have a few queries:

    1. What is the default noise level of the ADS9813 when using the two’s complement data format? We are observing a default noise swing of 50k on the channels. This noise disappears when an input is fed, but a 50k default noise level doesn’t seem normal.
    2. Can you clarify how many clock cycles the ramp test pattern takes to increment? We are observing that each count remains for 16 clock cycles instead of 1.

    Best regards

  • Hi CT,

    That is good news! What kind of general application/project are you using ADS9813 for?

    Regarding the noise, if plotting an FFT, depending on which input range, and bandwidth mode used, the SNR should be around 90.3dB. Front-end/system variables may introduce additional noise.

    Yes, it looks like ramp output increments after every 16th sample:

    Best regards,

    Samiha

  • Hello samiha,

    We are currently evaluating the performance of this ADC before finalizing it for our application.

    Regarding the noise, the issue is not related to SFDR. We are observing a noise level of 50k—could this be the ADC's default noise swing?

    Additionally, we have noticed that fclk is not aligning correctly with the data, even though sample_sync is provided. At times, the channel data appears to be circularly shifted, ( that is if we give input in channel 1 it is reflected in channel 2 or channel 3 sometimes).which we suspect is due to improper alignment between fclk and the data.

    How can we resolve this issue?

    Best regards

  • Hi CT,

    What do you mean by 50k? Could you please clarify units or share a plot please? You could try shorting the positive and negative inputs of the ADC channel to see if the noise is internal to the ADC.

    Are you providing SYNC pulse after power-up, with SMPL_CLK provided? Could you please provide a screenshot of oscilloscope or logic analyzer? SYNC must be provided anytime the SMPL_CLK frequency is also changed. 

    Best regards,

    Samiha