ADC3660: Please review ADC3660 programming.

Hi,

What do you mean sometimes working correctly and sometimes not?

Do you mean you get a valid data capture?

What data capture board to you have? What is the part number?

Please provide more details on what is going on.

Thanks,

Rob

Hello,

To allow us to debug your configuration, please provide the following information about the ADC configuration you are trying to use:

• Sample rate
• Are you using Decimation? If so,
  • Decimation rate 
  • Complex or real decimation
  • NCO Frequencies
• Output interface mode (1-wire, 2-wire, half-wire)
• Resolution
• Any other settings?

Best,

Luke Allen

Hello LUKE and Rob!

Sample rate: 63.456 MHz
Decimation Factor: 8
DDC setting: Complex
NCO frequency: 10.841 MHz (3561203106)
Output interface mode: 2-wire
Resolution: 16bit
FCLK Source Select :DEC
Symptom: SN sometimes deteriorates when setting is LOAD.

Best regards.

Miyahara

Hello LUKE and Rob!

How is the progress on the answers to my questions?

Hi Miyahara,

Sorry for the delay, let me look at this in the lab tomorrow.

What do you mean by Symptom: SN sometimes deteriorates when setting is LOAD.??

Regards,

Rob

Hi Miyahara,

Luke and I have looked at this in the lab, we are still working through a few more setup issues for the application specifications above.

I will give you an update on where we are at by the end of the day tomorrow.

Regards,

Rob

Hello LUKE

Hello ROB

Thank you for the analysis.
What I am doing is receiving a radio signal, capturing it into an FPGA with an ASDC3660, and evaluating it with demodulated audio. I would like to confirm if there is a problem with the ADC settings.

Bestregards

miyahara

Hi Miyahara,

Would it be possible for you to send over some data captures or FFT plots for us to understand the problem better?

Also, would it be possible you show us how your test setup is on the bench? Please send pictures and/or a block diagram with instrument details.

Thanks,

Rob

Hellow Rob

I have gone through the ADC settings here, imported the digital data of the FPGA input into MATLAB and FFT'd it when it was OK and when it was NG, and found that there is no difference.
I will do some more analysis on my end.
The current block is shown below.
I would like to know if there is a problem with the configuration data set in the ADC, so please respond.

Bestregard

Miyahara

Hi Miyahara,

Please help me understand this part of your sentence above "...when it was NG, and found..." What does NG mean?

Your block diagram is fine. If you can share the amp and ADC schematic portion, I can guide you if the amplifier is setup correctly.

I assume you want to DC couple the amp to the ADC? Is so, its important to setup the amp correctly to do that, otherwise, you could experience poor FFT data.

Please advise.

Thanks,

Rob

PS - we are validating your register writes on the lab bench with design. I hope to have an update by early next week.

Regards,

Rob

Dear Rob

I wanted to follow up regarding the validation of the register writes on the lab bench with the design. As of now, I have not received any updates, and I would appreciate any information you could provide on the current status.

Thank you for your attention to this matter, and I look forward to your response.

Bestregard

Miyahara