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ADS127L11: DRDY-pin is not getting low

Iouri Markin
Intellectual 650 points
Part Number: ADS127L11


Tool/software:

Hello,

we are working on design based on ADS127L11. ADC configured in "Synchronized control mode" with external sync pulse, 

and use DRDY pin as data ready indicator.  Problem what we are experiencing DRDY pin never goes "Low".

We did initial hardware check:

AVDD = 5V

VCCIO = 3V3

External clock = 25.6MHZ

Voltage @ pin1 (CAPA) = 1.6V; there is 1uF cap connected to this pin and GND

Voltage @ pin18 (CAPD) = 1.6V there is 1uF cap connected to this pin and GND

configure host SPI "MODE 1"

After power up we drive reset line "low"  for  2mS.

Then, sending SPI configuration data:

0x85 0x5B

0x86 0x10

0x88 0x80

Then, apply external sync pulse (to "START" pin) : period 20uS positive pulse width  391uS. DRDY pin always stays "high".

Question to TI experts: If there are anything we missed?

Please advise at your earliest convenience.

Thank you,

Iouri

  • 0
    TI__Mastermind 47970 points

    Hello Iouri,

    Have you looked at more than one board/ADS127L11?  If multiple boards, does this occur on all boards or just a single board?

    For debug purposes, after RESET, do not write to the registers and hold the START pin continuously high to see if the DRDY pin starts toggling (should be 400kHz).  If not, then there is a problem with the device.  

    The CAPA voltage of 1.6V is correct, the the CAPD voltage should be closer to 1.25V, not 1.6V.  The maximum voltage on either CAPA or CAPD is 1.65V; accidentally shorting either of these pins to the AVDD (5V) or IOVDD (3.3V) supply voltages will damage the device. 

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Intellectual 650 points

    Hi Keith,

    Than you for your reply. If I  keep start "high" without sending any SPI configuration data, I am getting DRDY signal 400KHZ.

    Also re-checked CAPA (pin 2)  1.62V CAPD (pin18) 1.31V. Looks like ADC is functions correctly,

    I am also attaching screen capture of SPI configuration data transfer, please see below.

    Please advise at your earliest convenience. 

    Thank you,

    Iouri

  • 0 in reply to Iouri Markin
    TI__Mastermind 47970 points

    Hello Iouri,

    That is good news that the ADC is working correctly after power-up.

    Looking at your timing waveforms, you are using the wrong SPI mode.  The SCLK must idle low, not high.  SCLK should be low on the falling edge of /CS.  The first rising edge of SCLK will launch the MSB on the SDO pin, and the next falling edge of SCLK will capture the MSB on the SDI line.

    Please change your SPI mode; I think this will help.   

    Since you are using the default register settings for the wideband filter, OSR32, and a standard 25.6MHz external clock, the data rate (and /DRDY frequency) should be exactly 400kHz, or 64 CLK cycles.  When using synchronization mode, the period must be equal to 64 CLK cycles, or any integer multiple of 64 CLK cycles, otherwise, the filter will reset.  If this is the case, /DRDY should continuously toggle at 400kHz, otherwise, you will see a series of /DRDY transitions, and then the filter will be reset and /DRDY will be idle for the latency time of 170.6u, before toggling again.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Intellectual 650 points

    Hello Keith,

    Thank you for detailed explanations.

    Two more questions:

    1. Could you please review updated SPI capture bellow. is it correct?

    2. If I get your explanations right: If we want to have sampling rate 50KHZ then we need to drive "Start" pin with  50KHZ signal and set OSR filter with 256(config 3 register), Does  it makes sense?

    Please advise at your earlies convenience.

    Thank you for all your support.

    Regards,

    Iouri

    SPI CFG

  • +1 in reply to Iouri Markin
    TI__Mastermind 47970 points

    Hello Iouri,

    The SPI timing have the correct mode polarity.  However, you should verify that your host processor SPI port is configured to capture data from the ADC on the falling edge of SCLK.  The only concern I have is the timing between the falling edge of /CS and the first SCLK rising edge, td-CSSC, which should be 10ns.  You may be meeting this requirement, but it is impossible to tell with the time scale in the pictures.  If you insert at least t-CLK period delay between /CS falling and SCLK rising, this will ensure all timing specifications are met.

    Setting OSR=256 with f-CLK=25.6MHz will result in a 50ksps data rate.  However, in this case, you can simply leave the START pin high; the ADC will continuously convert data at 50ksps.  You would then monitor the /DRDY pin for a falling edge, and then transfer the data.

    Unless you need to keep the ADC synchronized to an external event, you do not need to use synchronized control mode; simply leave the ADC in the default START/STOP mode after power-up and keep the START pin high for continuous conversions.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Intellectual 650 points

    Hello Keith,

    Thank you  for your reply. adding half of SCK cycle  between filing edge of /CS and first rising edge of SCK solved the problem. I am getting DRDY at 50KHZ.

    Thank you very much for great support.

    Regards,

    Iouri

  • 0 in reply to Iouri Markin
    TI__Mastermind 47970 points

    Iouri,

    Glad to hear it is now working for you.

    Regards,
    Keith