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ADC12QJ800: sampling clock delay going through PLL

david royle
Intellectual 585 points

Part Number: ADC12QJ800

Tool/software:

We have two ADCs receiving delay matched device clocks, then PLLs used to derive sampling clocks. Is there delay, or more importantly, temperature dependent, delay going through PLLs?

We are would like to know how much the PLL will contribute to mismatch in sampling time.

  • 0
    TI__Expert 6450 points

    Hi David,

    If both ADC PLLs are getting phase locked signals then each sampling clock generated by the internal PLLs will be aligned to each other. Now this is the ideal case where there is no routing mismatch or anything affecting the reference clocks into the ADC. This could introduce some sampling time mismatch which would also change over temperature. But in the worst case your sampling clocks for both ADCs would only vary by +-180 degrees in the worst case.

    Best,

    Eric

  • 0 in reply to Eric Kleckner
    Intellectual 585 points

    I am asking if there has been any characterization of the internal PLL regarding its input to output offset. Typically this would be due to offset in the phase detector which may be temperature dependent. (180 degrees of our sampling clock would be huge by comparison).

  • 0 in reply to david royle
    TI__Expert 6450 points

    Hi David,

    The ADC has some specs in its datasheet for sampling aperture delay from the clocks falling edge to the sampling instance for its clocking modes. This is only a typical number and is not specified against temperature.

    My previous comment was more talking about the routing mismatch ADC to ADC introducing mismatch to each adc.

    Thanks,

    Eric