Other Parts Discussed in Thread: LMK04828, LMK04826, DAC38J84
Tool/software:
Hi,
We are planning to prove multi DAC synchronization with our JESD IP. The current setup includes two DAC38J84EVM board, one LMK4828 eval board and one EFINIX titanium FPGA eval board. I have attached the setup diagram for reference.
- We are planning to use an external LMK04828 / LMK04826 Evaluation board as it can generate required phase aligned clocks and sysrefs for the secondary LMKs.
- Divider resetting will be used to generate synchronized device clock and sysref for secondary LMKs.
- Sysref: Continuous/ Pulsed Sysref will be generated from primary LMK. (For 5 Gbps, Sysref frequency = 3.90625 MHz).
- Secondary LMK will be operating in ZDM mode to generate synchronized device/sampling clock and sysref.
- Secondary LMK will not generate any sysref. It will just forward the incoming sync signal to the Sysref Path. Since there is D Flipflop in the path. External sync from primary LMK is phase aligned with the VCO of the secondary LMK before forwarding to the output.
- We will be using two FMC male to female cable to connect both the DAC EVM to single EFINIX eval board.
- There will be two separate JESD204B TX IP in single EFINIX eval board and the transmitted data from both the JESD TX IP will be received by the two JESD204B Rx IPs in two separate DAC38J84 EVMs and then will be checked on oscilloscope.
So before proceeding we want to confirm whether the current testing scheme is feasible and we are thinking in right detection.
Can test the Multi DAC synchronization with this setup ?
Please let us know if we are missing something.
