• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 159 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS127L11: ADS127L11: Frequency Shift on the acquired analog signal

ABHIJITH BENNY
Prodigy 40 points
Part Number: ADS127L11

Tool/software:

Hi Ti team,

We were observing a frequency shift on the data received from the ADS127L11 while giving a 10kHz sine from frequency generator we are able to observe ~65Hz shift (i.e . we are observing 10065 Hz after reconstructing the signal and taking the FFT.

The configuration used:

  • Wideband Filter with OSR 32
  • Input Clock frequency: 25.606MHz

We have checked the function generator and code for reconstruction of data with another board with similar implementation but different ADC, but it worked fine as expected.

  • 0
    TI__Mastermind 46610 points

    Hello Abhijith,

    The ADS127L11 data rate will be an exact integer number of input clock cycles.  In the case of WB filter, OSR32, the number of clock cycles per sample period will be 64.  I assume you are using an external clock source that you measured 25.606MHz, which equates to a clock period of t-CLK=1/25.606=39.05ns.  

    The /DRDY period should then be 64*39.05=2499.41ns.  I suggest measuring the /DRDY period to confirm if this is true.  If not, there are a few possible causes.

    1.  The external clock signal has a lot of ringing or very slow edges, resulting in some clock cycles getting missed or extra clock cycles resulting in timing errors.  If this is a case, usually adding a series resistor in the range of 10ohm to 50ohm will help.

    2.  Since you are using a 25.6MHz clock, it is possible that you did not correctly configure the ADC to use the external clock and it is actually using the internal 25.6MHz oscillator, which can be up to 0.8% error.  Double-check your code to make sure you are setting the CONFIG4 register (0x08h) CLK_SEL bit to 1 (default power-up is 0b, internal clock).

    Regards,
    Keith Nicholas
    Precision ADC Applications