Tool/software:
Hello everyone!
I have a doubt about the power consumption of the part at different clock frequencies. In the datsheet power consumption is detailed at a fclk of 27MHz. I plan on running the ADC at lower frequencies. Are there any data available about the power consumption vs fclk? Is there any formula I could apply?
Hello Raul,
The biggest reduction in overall power consumption is using the different modes of operation, where high-speed is the highest power mode and low-speed is the lowest power mode, as outlined in the datasheet.
However, as an estimation at different clock frequency, 100% of the DVDD current will scale with the clock frequency, and 15% of the AVDD current will scale. IOVDD changes very little and can be estimated as constant for a given mode.
As an example, the above current numbers are based on f-CLK=27MHz. If using f-CLK=20MHz in high-speed mode, you can expect the typical DVDD current to decrease from 23mA at 27MHz down to 23*20/27=17mA and AVDD to decreased from 97mA down to 0.85*97+0.15*97*20/27=93mA.
Regards,
Keith Nicholas
Precision ADC Applications
