ADS131E08: Issue Utilizing the Full Range

Hi Daniel,

I will look into the details and get it back to you soon, thnaks.

BR,

Dale

Hi Daniel,

Thanks for your patience.

First, I would clarify the input range. Your have a pseudo-differential input configuration. The differential input range is +/-Vref/Gain, so your ADC input range is +/-2.4V for Gain=1. Your ADC input range is +/-1.2V for Gain=2, not +/-2.4V as you thought.

I have few questions:

• Did you short DGND and AGND together on your circuit board?
• Did you change the data rate setting to 24-bit in the CONFIG1 register before you did the test? I hope you already turned on the internal reference buffer.
• Can you measure the voltage between the VREFP and VREFN? Can you measure Vmid? Using internal Vref for external circuit is not recommended, so I want to double check those signals since you have a buffer.
• Can you measure the internal MVDD and test signal by programming MUXn[2:0] in CHnSET register?
• Was your analog input voltage +2.4V for all positive Codes for both case 1 and case 2 in your table? Was your analog input voltage 0V for all Negative Codes in your table? 

BR,

Dale

Hi Dale, thanks for the reply. I will review this and get back to you with answers to your questions soon.

Hi again Dale. Apologies for the delay here - things are moving a bit slowly on this project at the moment, but I am working on gathering the info you requested and will write back as soon as I have it. 

Hi Daniel Mitchum,

Dale is actually out of the office, so our response would be delayed anyway for the next 1.5 weeks

-Bryan

Dale, before we continue the conversation I want to back-track and make some corrections to my statements and numbers. 

I said, "This way the differential input voltage range is +/-1.2V, and by using an internal ADC gain = 2 we achieve a differential input voltage range of approximately +/-2.4V."

I should have said, "This way our circuit provides a differential input voltage from +/-1.2V, which is less than the differential input voltage range of +/-2.4V at gain=1. By using gain=2, we bring the differential input voltage range to +/-1.2V and now our circuit is utilizing the full range." 

I see there was a gap in my understanding and I hope this correction clears that up.

Additionally, and to answer your question #5, the positive analog input voltage was not +2.4V as I stated. It was actually +3.3V for case 1 and +3.0V for case 2. I've verified that the positive count values align with these input voltages, and I corrected the value for case 1 at pga = 1. I also list case 2 again for reference.

As for the negative codes, the positive analog input voltage was truly 0V. I double checked this with new measurements. 

-

And I can give answers to your questions #1 and #3. I need to get with my firmware engineer and will get you answers to questions #2 and #4. 

1. Yes, AGND and DGND are strategically shorted in a few places around the board.

2. On both cases, VREFP to VREFN measure at 2.400V and VMID measures at 1.199V. 

With all this said and with the input voltages we provided, I would expect to see -4M for negative codes and +7M or +6M for positive codes at gain = 1, and +/-8M counts at gain = 2. We see expected behavior at gain = 1, but at gain = 2 the negative codes do not reach +/-8M. 

Hi Daniel Mitchum,

Thanks for your clarification.

Did you directly short the AINxP to the GND or use a signal generator to get 0V input for a negative differential input? Did you measure the voltage between AINxP and AINxN when the voltage on AINxP is 0V? Can you provide the RAW data directly from the ADC instead of negative codes?

BR,

Dale

Dale, normally AINxP is driven down to 0V through an opamp but I also tried shorting AINxP directly to AGND and got the same negative counts value.
For RAW data, are you asking for data in hex? 

To answer some of your earlier questions:
2. We are running in 24-bit mode since we are reading at 1kHz and we do have the internal reference enabled because we see 2.4V at the output and confirmed PDB_REFBUF is enabled. 
4. I measured the internal MVDD and test signal on the board used for case 2 for all 8 channels.

Hi Daniel,

Your measurement for internal MVDD on all channels are correct. "56CBAB" hex code represents ~1.62V that matches the voltage 0.5x(AVDD-AVSS) between MVDDP and MVDDN, "2BB888" hex code represents ~0.82V that matches the voltage DVDD/4 between MVDDP and MVDDN. The ADC worked as expected.

RAW data is the original conversion data from the ADC, hex or decimal format is ok. Please apply a DC voltage to AINxP, gain=2, please measure the differential voltage between the AINxP and AINxN, let me know your measured voltage and also share the raw data.

BR,

Dale

Dale, thank you for your patience on this request. I will get you data by end of week. 

Hi Daniel,

Sounds good.

BR,

Dale

Hey Dale, I measured between AINxP and AINxN by putting in ~1.2V into both inputs. The DC voltage I measured between them was -0.8359mV. Our firmware read this as 24-bit 0xffe4e3 in RAW data. 

On another vein, we've been working with some alternate configurations to improve our noise performance with this ADC. One of these configurations utilizes a 5V bridge supply and a 2.5V reference so we can utilize the full input range with a PGA gain = 1. In this configuration we supply the reference signal as an input rather than use it as an output for our bridge supply.

Performing the same test on this 5V configuration, where AINxP is shorted to 0V, we do not see the same issue with the negative counts getting "stuck." The values go right to -8M whereas they get "stuck" at -4M on the 2.4V bridge supply version.

I hope this additional info can help identify the root cause. 

Hi Daniel Mitchum,

We were unable to review your feedback today, we will get back to you early next week. Thanks for your patience.

-Bryan

Hi Daniel Mitchum,

Thanks for your patience.

1. When you measured between AINxP and AINxN by putting in ~1.2V into both inputs, both AINxP and AINxN pins are shorted, so the differential input voltage should be 0V, why and how did you measure -0.8359mV between those two pins? 

 The voltage for your 0xffe4e3 code= -6904*1LSB=-6940*(2.4v/2^23)=-1.98mV when the Vref is 2.4V, so the is a correct conversion result for -0.8359mV analog input voltage if the gain setting on the ADC is 2.

2. When you said "In this configuration we supply the reference signal as an input rather than use it as an output for our bridge supply." did you use the internal 2.4V as the excitation voltage to your bridge? From your schematic, you did not mention this before and I thought you only used this 2.4V Vref to generate 1.2V voltage(VMID) for the AINxN input pins. In order to debug and identify the root cause, just use a DC signal source for ADC's input, disconnect the Vref from other circuits to make the test simple. The internal Vref can not provide too much current to drive other circuits even a buffer is used. 

- Dale

Dale, here are my responses to your questions:

1. The voltages were not from the same source. AINxP was created from a resistor divider on a mock-transducer board connected to the main board, whereas AINxN was created from the VMID voltage divider close to the ADC. As a result, the voltages were not exactly the same. 

2. Sorry for not being explicit before. 2.4V from internal Vref does indeed get used as the bridge supply. If you look closely, you'll find the net label at the output of the buffer and before the divider to 1.2V. When you say to disconnect Vref from other circuits, do you mean all circuits except VMID as an input for AINxN or all circuits including VMID? 

Hi Daniel Mitchum,

1. As you can see my calculation in the previous response, the conversion code you got matches the input voltage you measured. I did not see any issue.

2. Thanks for your clarification. When 2.4V is used as the bridge supply, the common-mode voltage of your signal from the bridge is 1.2V. The minimum common-mode voltage is 1.3V when the AVDD – AVSS = 3.3 V, gain = 2, and VMAX_DIFF = 1000 mV as you can see the section 9.3.4.1 Input common-mode range in the datasheet. Is the configuration of 5V AVDD and 2.5V Vref available in your design? if so, just use this configuration.

-Dale

Dale, 

We will go forward using the 5V AVDD and 2.4Vref configuration. Is it safe to say our early saturation issue can be attributed to operating outside of the common-mode voltage range?