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ADC08DJ5200RF: sampled data is incorrect

Han Xiangqun
Prodigy 20 points
Part Number: ADC08DJ5200RF


Tool/software:

I use TI's ADC08DJ5200RF chip for data acquisition. Now I find that the sampled data is incorrect, so I use the built-in JTEST of the chip to conduct data testing from the ADC to the FPGA. When using K28.5, the data collected by the FPGA is unstable. What could be the possible reasons?

  • 0
    TI__Expert 6210 points

    Hello Han,

    This looks like there could be an unstable clock to the ADC or FPGA, such as the sampling clock to ADC or reference clocks to the ADC. All clocks should be phase locked to ensure they do not slip. 

    Can you share some more details such as is this a custom board you have designed or the EVM? Which JESD IP are you using TI JESD IP or Xilinx? Lastly can you share how you are programming the ADC.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 20 points

    Hi, Eirc. This is a custom board. The JESD IP I used is Xilinx's JESD204 IP.

  • 0 in reply to Han Xiangqun
    TI__Expert 6210 points

    Hello Han,

    I am not familiar with the Xilinx IP you will have to contact them for support on their IP. But the problem still looks like a clocking problem with the ADC. Can you report the Status of register 0x208 on the ADC this will help us debug if it is an ADC issue.

    Best,

    Eric