AFE58JD48EVM: clock tree : purpose of the CDCM1802 component

Tool/software:

Hi,

I would like to understand the clock tree of the AFE58JD48EVM : What is the role of the CDCM1802 component?

The JESD interface between the FPGA and the AFE is  the subclass 1 configuration.

The LMK04826 has two clock outputs : one 120 MHz clock named FPGA GTX (120MHz) and one named LMK ADC CLK clock (480MHz). Then the LMK ADC CLK clock is divied by 4 with the CDCM1802 component  to do the AFE's ADC clock (120MHz).

I understand that the LMK04826 can generate a 120 MHz clock. Why is the AFE ADC's clock not connect directly to the output of the LMK04826 component ?  I don't understand why the CDCM1802 is mandatory.

Thanks,

Jerome