LMP92066: LMP92066 Configured For GaN Mode of operation during Power OFF negative spike observed.

Hi Upendra,

Is this the DAC output or the FETDRV output? The DAC output has some glitch during POR, but if FETDRV is connected to VSS you shouldn't see a glitch. Could you send a capture of the VSS signal during this time as well?

Thanks,
Erin

Hi Erin,

we observed the same spike of -2.5V level at FETDRV Output and VSS as well.

When we added series 20ohm resistor in VSS Pin before 10uF Capacitor, we observed negative spike reduced to -4V in VSS but it remains at -2.5V level at FETDRV output.

Hi Upendra,

When you shut down the VDD, what is the value of your DRVEN pin? Is the FETDRV output connected to VSS or DAC when you shut down?

Thanks,
Erin

Hi Erin,

DRIVEN pins are set to zero volt and the FETDRV output is connected to VSS during shutdown.

Hi Upendra,

Could you potentially send us a scope screenshot showing VSS, DRVEN, FETDRV, and VDD during shutdown? Additionally, could you send a screenshot of device schematic?

Thanks,
Erin