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ADC3664EVM: DCLK and Sampling Clock

ttd
Mastermind 8620 points
Part Number: ADC3664EVM
Other Parts Discussed in Thread: ADC3644EVM,

Tool/software:

Dear Technical Support Team,

Accoriding to userguide, DCLK and Sampling clock input level should be ＋10dBm.

Which is correct to set sinewave(10dBm=2Vpp) or square wave(Vpp=1.414Vpp) from external pulse generator?

My function generator cannot set 437.5MHz square wave.

Userguide describes sampling clock and analog input is requre to get a good performace.

 Does it mean signal generator setting? or implement it on the board circuits?

If you have any example, could you share it?

Best Regards,

ttd

  • 0
    TI__Mastermind 39570 points

    Hi TTD,

    There is an error in the user guide. Please use a sinewave and set the level to 0 to +2dBm max.

    For the DCLKIN, you can use a function generator if this is clean enough. However, its best to use good quality low jitter (clean) signal generators.

    Some examples include the SMA100A or SMA100B from R&S, or Agilent 8257D. Any of these choices, needs to have the low jitter option installed.

    Each of these signal generators, needs to have a bandpass filter installed in-line from the output of the sig gen to the input SMA connector on the EVM.

    Here is a generic pic.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Mastermind 8620 points

    Hi Rob,

    Thank you for your reply.

    I got the insertion position for BPF your showed.

    Is 2dBm(0.796Vpp sinewave)  max for DCLIN(650mVpp max)?

    The VID for CLKP/M for sample clock is 1Vpp(typ) and 3.6Vpp(max). 

    It seems that with 2dBm(0.796Vpp) is not enough level. 

    If my understanding is not correct, could you advice it?

    I have another question about ADC3644EVM(CMOS interface).

    My configuration is bypass mode, then ADC3644EVM doen't require external clock for sampling clock and DCLKIN?

  • 0 in reply to ttd
    TI__Mastermind 39570 points

    Hi TTD,

    The CDC on board clocking chip does not support all sampling clock rates.

    What is the sampling clock rate you are using? 437.5MHz? 

    I will set this up tomorrow on in the lab to check.

    If there are any other register write or configurations, please send those along too, so I can verify on the bench.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Mastermind 8620 points

    Hi Rob,

    Sorry for confusing the slightly different parts number between ADC3664 and ADC3644.

    I already have a ADC3664EVM(SLVDS) and  ADC3644EVM(DDR CMOS) .has been shipping now from TI(I don't have it yet).

    ADC3644EVM(use DDR CMOS,14bit, bypass) supports 125MHz sampling clock on board clock(CECE6214) based on datasheet.

     *ADC364xEVM User's Guide

    My understanding is that  ADC3664EVM(SLVDS)  doesn't support CDC(require external clock).

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 39570 points

    Hi TTD,

    Actually for best performance and flexibility, my recommendation would be to use the external clock option for both EVMs.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Mastermind 8620 points

    Hi Rob-san,

    Thank you for your support.

    I got external clock is the best.

    Best Regards,

    ttd