Tool/software:
We are using the TI_JESDC IP for receiving data from from ADS52J90 in 4 lane mode and 32 channels.
Number of frames per multiframe has been set as 4 (K value = 4-1 = 3 is set in respective registers.
We have set the data packing as per Table 22. Data Packing in Normal Packing Mode for NAL = 4 and NSER > NRES in (page 55 of ADS52J90 datasheet).
Question regarding this format: The very first frame that comes along with LMFC is supposed to be ODD (ADC_in_1 i.e ADC_odd)) frame? We see that the with every reset in JESD, the odd even input is selected randomly.
Another question is regarding TX_TRIGG. We do not see TX_TRIG mentioned to be used in JESD mode. Do we need to use TX_TRIG for the even odd bifurcation while the JESD link is up.? We see that even with
"MASK_TX_TRIG" on reg 0x46 is set high, the ADC0, ADCe are still toggling on trigger. This is also not consistent. I request TI team to suggest please as datasheet does not clearly mentions about this.
We tried setting JESD_RESET1, JESD_RESET2 and JESD_RESET3 bit high as well but does not help.
Thanks,
Trushal
