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DAC39RF10EVM: Question About TI204C-IP

tabe
Prodigy 70 points
Part Number: DAC39RF10EVM

Tool/software:

Dear TI team,

I am reaching out to inquire about the TI204C-IP. I am planning to connect the DAC39RF10EVM to the VCU118 using 64b66b JMODE10, outputting 2-channel 12-bit data to the DAC over 16 lanes. The data sampling rate is 5Gsps.

Using the transceiver wizard, I generated two 8-lane cores. I assigned the following lanes:

  • Core 1: X0Y4, Y5, Y8, Y9, Y10, Y11, Y12, Y13
  • Core 2: X0Y14, Y15, Y24, Y25, Y28, Y29, Y30, Y31

Could you confirm if this configuration is correct? Also, the clock is divided into two systems: Bank120, 121, 122, and Bank125, 126 from different SLRs. However, Bank122 is shared between Core 1 and Core 2. Would this cause any issues?

Since the DAC39RF10EVM can be connected to the TSW14J59 board under these conditions, I would appreciate it if you could explain how they are actually connected and operating.

Additionally, based on the reference design, I attempted to implement only Core 1 with 8 lanes under the above settings. However, after de-asserting tx_sync_reset following master_reset_n, tx_lane_data_ready does not assert, and data transfer does not start.

Furthermore, when I set NUMBER_OF_REFCLK_BUFFERS to 1 and Number_OF_QUADS to 3, qpll1_locked only returns 1.

Could you provide guidance on these issues?

I appreciate your support and look forward to your response.

Best regards,

tabe

  • 0
    TI__Intellectual 2280 points

    Hi Tabe,

    I will recommend creating a single 16 lane JESD IP instead of two 8 lane IP cores. This is because it is not easily possible to share a Quad/Bank between two cores. Each core generates a separate transceiver for itself, which will lock up the QPLL and Bank.

    The reason you are seeing QPLL1_locked return 0x1 is because the reference clock input to the transceiver will be a three bit bus, and you have a single reference clock buffer. In that case, you need to connect the same buffered clock to all three reference clock inputs. You have probably connected it directly, so only the lowest Quad is getting a reference clock (and hence only that PLL is locked).

    Regards,
    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 70 points

    Hi Ameet,

    Sorry for my late reply. I thought the JESD IP was limited to 8 lanes.

    Currently, the DAC39RF10EVM + VCU118 setup is at the customer’s site, so I can’t test it directly.

    I'll report back with the results once I'm able to implement it.

    Regards,

    Tabe