ADS127L11: Output data problem

Hello Iouri,

Are you properly converting the 24b value from 2's complement?

Please note that with an input voltage of 0V, the expected output code will be 0x000000h.  However, with noise, a slightly negative value will produce a code near 0xFFFFFFh.

Could you provide the ADC codes verses the calculated input voltage?

Regards,
Keith Nicholas
Precision ADC Applications

Hello Keith,

Thank you for your reply. Please see sample data bellow. I am also attaching log file

To convert data from unsign to sign number, using follow code 

Thank you,

Iouri

for i = 1 : length(bufferIn)
    if(bufferIn(i) < 8388608) % 0x800000
        bufferOut(i) = bufferIn(i);
    else
        bufferOut(i) = (16777215 - bufferIn(i) - 1) * (-1); % 0xFFFFFF
    end    
end

volts = (bufferOut / (2^23)) * 2.5;

b.txt

16777172
16777168
16777192
16777171
16777166
16777199
16777148
16777176
16777180
16777151
16777193
16777166
16777152
16777183
16777153
16777163
16777176
16777191
16777162
16777150
8388609                               // Artifact
16777148
16777167
16777202
16777162
16777190
16777158
16777176
16777178
16777153
16777180
16777165
16777185
16777181
16777153
16777179
16777156
16777185
16777197
16777179
16777170
16777145

Hello Iouri,

I believe your math has a mistake, but that does not explain the negative full scale reading artifact.

The following line is not correct.

bufferOut(i) = (16777215 - bufferIn(i) - 1) * (-1); % 0xFFFFFF

You should change it as follows (assuming your array is a 32b signed integer):

bufferOut(i) =  bufferIn(i) - 16777216; % 0xFFFFFF

You may have a timing issue on how you capture the data.  I suggest using a logic analyzer or scope to measure the SPI lines, including SCLK, SDO, /CS, and /DRDY, similar to Figure 6-2.  Please capture at least 2 SPI frames.  You do not need to capture the frame with the bad data; I am interested in looking at the timing between all of the data signals.  Also, during data capture, the SDI should remain low.

Regards,
Keith

Hello Keith,

Thank you for your reply. Please see captures bellow. Please note SDI (line towards ADC is low)

channel 4 blue is DRDY

channel 1 yellow is CS

channel 2 light blue SCK

channel 3 pink SDO (line towards to FPGA from ADC)

Please advise at your earliest convenience

Regards,

Iouri

Hello Iouri,

The timing looks good.

Please verify that you are using SPI mode 1.  In this mode, your MCU SPI should be capturing data on the falling edge of SCLK.  (The first SCLK falling edge will be the MSB.)  If you are capturing data on the rising edge of SCLK (SPI MODE 0 with SCLK idle low), then this could explain the glitch in the data that you see.

Some additional tests if you have confirmed SPI mode 1 with your SPI port configuration:

With AINN=2.5V, set AINP=3.5V.  Do you get the approximately correct value?  Are there still glitches?

Win AINN=2.5V, set AINP=1.5V.  Do you get the approximately correct value?  Are there still glitches?

Regards,
Keith

Hello Keith,

Thank you, for your reply. I think I had a defective part, ie I replaced ADC and glitches are gone,

also, I can confirm data from ADC SPI is getting latched on filing edge of SCK line.

But something still doesn't makes sense, I I follow your advise regarding biasing ADC inputs, please see results bellow

Vn = 2.5V DC; Vp = 1 V DC, getting roughly -.03VDC

Vn = 2.5DC Vp = 2.5VDC getting roughly  -2.5V DC

Vn = 2.5DC Vp = 3.5VDC getting roughly  -2.2V DC

Can you please advise what can be wrong

Thank you very much for all your support.

Regards,

Iouri

Hello Iouri,

I assume you are connecting the VCM pin to AINN (Vn)?  Do you have the VCM output enabled?  Using a DMM connected to ADC ground (I assume you are using a single 5V supply for AVDD1/AVDD2), please confirm the voltages on the AINN and AINP pins.  Some external power supplies can only source current and may not properly drive the ADC inputs.

Please provide a schematic that shows the ADS127L11 and all components connected to it, including the reference, input amplifiers, clock, power supplies.  Also, please provide a picture or sketch showing how you are connecting the external power supply to the ADC inputs.

Regards,
Keith

Hello Keith,

Thank you for your reply, please find attached schematic.. To do the test I have removed R9, R14;

Using external dual power supply:

connect CH1 of the power supply to negative input of the ADC (p5) and set  to 2.5V DC

connect CH2 of the power supply to positive input of the ADC (p4) and set to 1.5V DC, 2.5 DC, 3.5V DC

Also, checked both inputs with DMM looks fine.

Thank you for all you support.

Regards,

Iouri

3441.ADC.pdf

Hello Iouri,

It seems like the inputs are floating when you take the measurements.  Can you confirm your external power supply grounds are both connected to the local ground on the ADS127L11 board?

With ANP(4)=3.5V and ANN(5)=2.5V, the ideal conversion code should be (3.5-2.5)/4.096*2^23=2048000, or 0x1F4000h.

Regards,
Keith

Hello Keith,

Thank you for your reply. I have checked voltage@ pin4 3V5 DC and pin 5 2V5 DC, I was using DMM,

also board GND is connected to GND of the power supply. Still getting similar plot, please see bellow.

I am thinking: would it makes sense to extend time between CS filing edge and first rising edge of SCK,

add like half cycle SCK delay between? Please advise at your earliest convenience 

Thank you,

Iouri

Hello Iouri,

Your SPI communications look correct.  No concerns with the timing margins.

I think you still have something wrong in hardware.  Maybe double check on connections to the ADC; verify voltages on the actual pins of the device.

Otherwise, I cannot think of anything else to try.  Maybe you have accidentally damaged the ADC while working with it.  If the CAPa pin is accidentally shorted to the AVDD pin, this will damage the device.

Regards,
Keith

Hello Iouri,

Setting Vn=2.5V and Vp=3.5V, please capture a full SPI frame, similar to before.  I can double check to see if the ADC code is correct.  If it is not correct, then you have a hardware problem.  If the code is correct, then you have something wrong in your code.

Vn = 2.5DC Vp = 3.5VDC getting roughly  -2.2V DC

Regards,
Keith