ADC12DJ2700: Gain trimming between ADC-A and ADC-B in Single Channel mode

Hi Thorsten,

I am checking with design on this for you. Please give me a few days to respond.

Regards,

Rob

Hi Thorsten,

When measuring the 1-3LSB difference, is this with an analog input frequency applied? Or just looking codes with an unconnected analog input?

Also, is the DC coupled amplifier still connected when measuring this offset?

Please let me know.

Thanks,

Rob

Hello Rob,

we're measuring the input without any frequency applied. INA is driven by an LMH3401 (SE-Diff conversion) that is always enabled. The SE input leg to the LMH FDA is terminated with 50R to GND. The other leg of the LMH receives a DAC voltage for application specific offset adjustments.

After the initial foreground and offset calibrations, we get about 2.5LSB (which is perfectly fine for the application) standard deviation around the ADC midscale value 2048.

After shifting the baseline, each ADC-x core (splitting the resulting data stream into two alternating buffers) is still converting the input at ~2.5LSB std dev. But the 'center' values for each core have 'drifted' around 1-3LSB apart from each other.

Thanks,

Thorsten

Hi Thorsten,

I am sorry, but I do not understand you comment here: After shifting the baseline, each ADC-x core (splitting the resulting data stream into two alternating buffers) is still converting the input at ~2.5LSB std dev. But the 'center' values for each core have 'drifted' around 1-3LSB apart from each other.

Also, I verified from design the resisters that were mentioned in the datasheet, were in error. There are no registers in order to change or modify the gain and offset for this ADC. I apologize for the confusion. We are correcting the datasheet to remove this section.

Regards,

Rob

Hi Rob,

in each scenario we're acquiring 500k samples at 5GSps. Also, we're splitting the same trace into two 250k sample buffers like so:

Buffer 1: Sample 0, 2, 4, 6, etc...

Buffer 2: Sample 1, 3, 5, 7, etc..

Our assumption: Buffers 1 and 2 then each hold the samples converted by each active ADC core.

Then we're histogramming the original and both of the split buffers to get mean and standard deviation values for each.

Setup:

We're feeding a DC voltage through the LMH3401 FDA into the ADC (by means of the above mentioned offet DAC).

Scenario 1: 0V

We're letting the ADC perform an offset calibration, then take a 500k sample trace (top left).

Combined Buffer (top left): mean: 2050, std dev: ~2.5 (top middle)

Buffer 1 and Buffer 2 (both traces overlayed red/blue, bot left): the same as the combined buffer (bot middle, bot right).

Scenario 2: 200mV (results in a converted ADC value of ~100)

We're not re-running any calibrations, then take a 500k sample trace.

Combined Buffer: mean: 100, std dev: >3

Buffer 1: mean 98, std dev: ~2.5

Buffer 2: mean 102, std dev: ~2.5

We can also observe this behaviour near the other end of the input range, just with a flipped orientation between buffer 1 and 2.

I hope this makes sense.

I understand, that there are no means to adjust the gain per ADC core. That would have been an explanation as to what we're seeing here.

Thanks,

Thorsten

Hi Rob,

okay, thank you for the insight. We'll have to see how we can work this into the application, since the hardware design ist already done. I'll take a look at the recommended ADC.

Thanks,

Thorsten