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TI-JESD204-IP: Simulation with QuestaSim

Mariano Mate
Prodigy 10 points
Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADC14X250

Tool/software:

Hi,

my project connects a ZCU102 with an ADC14X250 EVM. After configuring the IP to match the ADC features (8b10b, 1 Rx lane, 5 Gbps lane rate, etc.), the next step is to develop the application layer. For that the plan was to connect the Tx and Rx ends of the TI-JESD204 IP in loopback in simulation together with the application logic.

However I am running into issues running the TI-JESD204 IP Questa simulation model. However, both cpll and qpll outputs always remain in high impedance ('Z'). I tried adding the simulation libraries for the Xilinx GTH transceivers to my Questa environment but that did not help either.

Some information about my simulation setup:

- mgt_freerun_clk runs at 100MHz
- mgt_refclk_p/n run at 156.25MHz (same as in the zcu102 8b10b reference design)
- Both sys clocks run at 156.25MHz (same as in the zcu102 8b10b reference design)
- master_reset_n held low for 200ns, then high
- Simulation runtime 200us

Is this QuestaSim simulation workflow fully supported or does it have limitations?

Thanks
--
Mariano Maté

  • 0
    TI__Intellectual 2340 points

    Hi Mariano,

    The TI JESD IP is internally regressed using the Vivado and Cadence tools, so it is not exhaustively tested for Questa. However, we have a number of customers using Questa with no issues, so I am guessing this may be an issue with the simulation setup. Yes, you do need to ensure that Questa pre-compiled Xilinx libraries are included in the simulation flow. However, if the PLL outputs always show 'Z', this could be a connection problem.

    Please confirm if Vivado simulations with the same design work correctly. That will be one way of isolating if the issue is with the design or the simulation flow.

    Regards,
    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 10 points

    Hi Ameet,

    thanks for your reply. On Vivado I can simulate the original zcu102_8b10b reference design with 8 lanes and 64 bits per lane. However, when I configure it down to a single lane and 32 bits to reflect the characteristics of the ADC14X250M something around the transceivers seems to be odd in simulation. I've used the same force commands to stimulate both the 8-channel and the single-channel simulation.

    This is my transceiver configuration, using only one Quad and one channel:

    And this is what 1ch simulation looks like:

    Regards
    --
    Mariano

  • 0 in reply to Mariano Mate
    Prodigy 10 points

    Hi Ameet,

    my issue is more or less solved now. The cause seemed to be changing the Tx/Rx lane widths to 32 bits down from 64 bits. I changed them in both the transceiver config as well as in the verilog header file.

    Everything works fine if I keep the lane width to 64-bits. I should be able to make do with this, but I would like to understand why, given that the IP docs state that 32-bit widths are supported.

    Thanks
    --
    Mariano Maté

  • 0 in reply to Mariano Mate
    TI__Intellectual 2340 points

    Hi Mariano,

    I am not quite sure why you have run into this issue. The JESD IP supports both 64 and 32 bit widths on the transceiver lanes. Please let me know all the modifications that you made to the design.

    Regards,
    Ameet