ADC3910S125: Confirmation that falling clock edge not needed for single channel interface

Cameron Wutzke

Part Number: ADC3910S125

Tool/software:

We are using ADC default settings.

Can you please confirm that the nDCLK (falling clock edge) would not be needed for the single ended configuration. It seems like DDR mode is needed for dual channel devices, but it’s not clear if the nDCLK is needed on a single channel interface

over 1 year ago

+1 Geoff Roth over 1 year ago

TI__Expert 5660 points

Hi Cameron,

Could you please clarify if you are talking about SDR mode or having a single-ended DCLK. You interchanged several terms and I just want to make sure I understand what you are referring to.

Regards,

Geoff

0 Cameron Wutzke over 1 year ago in reply to Geoff Roth

TI__Expert 4687 points

Ah-

We discovered the issue. The single channel part still defaults to DDR where Channal A is the 1^st cycle and Channel B is the 2^ndcycle. We setup our FPGA to latch on the falling edge of the clock so, we were getting “0’s” every time.

Thanks

Data converters

Data converters forum

ADC3910S125: Confirmation that falling clock edge not needed for single channel interface