Tool/software:
Hi
We have designed a PCB that includes only a single ADS52J65 ADC. After loading the XC7Z045 FPGA with ADS52J65 firmware, the JESD204B are looking good.
I want to configure the platform to work with this setup, using 1 lane for data capture from the single ADS52J65 ADC.
After ADS52J65 is configured with ADS52J65_JESD_1L_160X_80_12.8Gbps(JESD 1-Lane mode),the D1,D2,D3,D4,D5~D8 lanes on ADS53J65 are turned on.
But the FPGA can't be arranged the 8-channel ADC in sequence.
I can reproduce the above-mentioned phenomenon, with to reconfigure or power cycle the system.
Could you provide guidance on how to modify configurations to ensure 8-channel D1~D8 linkup in sequence operation.
Thank you
Eddie