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ADS1246: Writes to register failing on initialization sometimes

Part Number: ADS1246
Other Parts Discussed in Thread: ADS124S06

Tool/software:

Hello,

I am seeing random failures on a write to the part in my initialization routines.

All reads always work.

Once initialized - everything works.

However, the write to register Reg3_SYS0 does not always work.


    setting = ADS1246_GAIN_32 + ADS1246_SPS_80;    // Actually 50 with special clock rate

     ADS1246_WriteReg( pCXT, Reg3_SYS0, setting );      

     result = ADS1246_ReadReg(pCXT, Reg3_SYS0);

        if(result != setting)
        {
            status = false;
        }

Any suggestions ?

  • Hi James Sullivan73,

    Can you provide logic analyzer captures showing an example of "bad" communication and "good" communication? Maybe this is a timing issue that isn't obvious just by looking at the code

    -Bryan

  • Hello - I set up the logic analyer and sometimes no errors, and after reset then many errors.

    Here is a screen shot of an error condition - everything looks great - except the part is ignoring me...

  • Hi James Sullivan73,

    Can you confirm the SCLK and CLK speed you are using (if you are using the internal clock then CLK speed = 4.096 MHz)?

    Can you also make sure the data is launched on the rising edge of SCLK from your controller so that the ADC can capture on the falling edge?

    There is no obvious reason why the ADC would occasionally have issues writing to one, specific register.

    -Bryan

  • Clock polarity is confirmed correct.

    SCLK is 1 MHz - A2DCLK is 2.56 MHz

    once it is initialized - it works. All reads work.

    I checked the states and timing of ResetL and StartA2D (which must be high to write registers)

    I will monitor it for now, my retrys  on start-up fix the problem, it just seems odd...

    Signals all look clean on the scope and logic analyzer.

  • Hi James Sullivan73,

    Thanks for providing the requested information

    The only other thing I noticed is that time between the last SCLK falling edge and CS high is small.

    This spec depends on your clock frequency, which has a period of 390ns. Therefore you need 7*390ns = 2.73us minimum to meet this threshold. I cannot exactly tell from the picture you sent but it seems possible that the delay is very close to this time. So my only other recommendation would be to either increase this delay time in your code, or increase the CLK speed, to see if that makes any difference

    -Bryan

  • I measured the time , and it was out of spec.

    I increased the delay - so far I have not seen the problem !

    That is a very interesting timing spec - I have not run into that before.

    I will continue testing tomorrow, before I call it resolved.

  • Hi James Sullivan73,

    Understood, let us know

    I'll also point out that we have released the next generation ADS124x device several years back, which is the ADS124S06. The ADS124S06 has more features and better performance compared to the ADS124x devices, and is offered at a similar price point, in case you are interested for future projects

    -Bryan

  • Thanks Bryan,

    I am using x3 ads1246's for simultaneous sampling, so a multiplexed device is not as helpful.

    I have not seen the problem reoccur since I corrected the timing.

    So thank you for the help !!