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ADC3562: Regarding the timing when Sample N sampled by the sampling clock is output from DA0/1

Part Number: ADC3562

Tool/software:

Hi

I don't quite understand how to interpret the timing diagram in Figure 7-1 on page 26 of the data sheet.

Starting from the falling edge of the sampling clock, data DA0/1 is output along with DCLK, and it is written as Sample N-2.

Am I correct in thinking that the data being output is the sample value going back two samples from the most recent?

Considering the signal conversion time of Tconv, it seemed natural that Sample N would be output on the falling edge of the next sampling clock.

In other words, "Sample N-2" in Figure 7-1 becomes Sample N-1, and "Sample N-1" becomes Sample N.

According to the specifications, sample N is output with a delay of two periods of the sampling clock, so just to be sure, we want to check whether this is correct.

Best Regards, Oda