Tool/software:
Hi,
I would like to confirm available update cycle for DAC register.
My customer would like to update 8ch DAC at the same time.
To realize this, I understood that user need to write eight DAC register to store desired value and after that user send "LDAC" trigger to apply setting to DAC analog output.
What I would like to confirm is following my understanding is correct to realize fastest access.
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* User use 50MHz (maximum SPI clock setting) as SPI clock with VIO = 2.7 to 5.5V.
* In this case, fastest access time for 1ch is below.
15ns(min of tcshigh) + 20ns(min of tcss) + 20ns (1cycle of 50MHz) x 24(24bit data) + longer settting of 10ns(tcsh) or 10ns(tsdih)
= 525ns
To calculate total of 8ch, we need to multiply 8 for above.
525 * 8 = 4200ns
Finally, need to send LDAC trigger
4200 + 525 = approx. 210kHz
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Could you please confirm above my understanding is correct ?
(Of cource, this is from viewpoint of DAC itself. No consideration system itself.)
Best Regards,
