ADS8688: Reading same value on all channels

Hi Simon,

Your schematic for the ADS8688 looks OK and I don't see anything obviously 'wrong' in the logic analyzer captures.  Is this issue happening on multiple boards?  Assuming you have a proper PCB and not a proto-board, can you verify that the RST/PD pin is high and that you have the reference voltage present at REFIO?

Hey Tom, 
Thank you for checking and confirming the schematics.
The circuit is assembled on a PCB propperly assembled . The behavior is on all the the seven boards tested so fare the same. Occasionally after a power cycle one is doing the acquisition as expected. But that behavior is not consistent.

The RST-Pin is constantly high during data acquisition, it is pulled low only during boot up phase. The REFIO voltage is about 4.085V measured with a multi-meter on different samples. Could that be a reason? But why if it is regulated ADS internally?

No Simon,

the reference would not cause this behaviour.  It sounds like you are in standby mode.  Can you try setting /CS high immediately after the 32-bit transfer and then toggle it low just before you start the frame?  It looks like you simply toggle it high just before each transmission.

Hey Tom,

Today I could modify the FW and adapted the #CS signal. Chip select is now only set to active durcing SPI clocking phase.

SPI CLK 5MHz

But unfortunately it did not help. In the example above the constant respons value over all 8 channels is alwise 0x0771. It changes to a different value only, if I repower the device.

I was also playing with the SPI clock frequency, two of the boards work as expected when I decrease the clock frequency (10MHz -> 5MHz), but the others still remain in this strange state without ADC aquisiton even if I go further down.

SPI CLK 10MHz

So the summary is:

The configuration register can always be written and read as expected on all 7 boards regardless of the clock frequency tested.

Adjusting the #CS did not cause any changes.

At 10MHz SPI clock, one of the seven boards occasionally delivers the analog data after a power cycle.

At 5MHz, the above board and another board work as well as expected and provide reasonable ADC values depending on the channel.

No changes at 2.5MHz and below. Still 2 out of 7.

What confuses me is:
- The configuration register action works on any device regardless of clock frequency, so SPI communication seems to be basically fine. But the analog data acquisition is somehow stuck.
- The previous prototype boards (with maginally different layout) worked fine with the FW described in the first post.

Thanks for your support, I appreciate any ideas and input.

Can you grab screen shots of the COMMS with an o-scope versus the logic analyzer?  If your SPI interface is noisy, that might be the issue and the logic analyzer won't necessarily show that level of detail.

Hi Tom
Unfortunately I hit the worng button. The issue is not solved yet.

The SPI singal curves viewed with the oscilloscope do not look as clean as the logic analyser ones (as expected ;-) ). But also not that wors that they can't be interpreted.:


before the digital isolator (MCU side)
Clock (y) and MOSI (g)



Clock (y), MISO (g)


after the digital isolator (ADC side)
Clock (y), MOSI (g)



Clock (y), MISO (g)


The screen shots above are from the 5MHz clock configuration, the signal look predy much the same for 10MHz clock.

Hi Simon,

It looks like the delay through the isolator might be impacting how the ADC responds to commands.  Can you focus on the ADC side and verify that you are meeting the setup and hold timings of SDO?