Tool/software:
Hello TI team,
I am working with the ADC3583 and need clarification regarding the use of the DCLKIN (DCLKINP/M) pins.
I am using the device in the following configuration:
- Sample clock: CLKP/CLKM = 40 MHz differential input
- Output mode: 2-wire SLVDS
- Resolution: 16-bit output
- Channels: Only channel A active (DA0/DA1 used)
- SPI configuration: Custom (no reference to DCLKIN usage)
I would like to use only the internally generated DCLK (DCLKP/M output) and leave the DCLKIN pins unconnected (floating or NC).
However, I couldn't find a definitive statement in the datasheet that confirms whether the device will function correctly **without an external DCLKIN** input.
My questions are:
1. Is **DCLKIN required** for normal operation in single ADC applications?
2. If not, can I rely on the **internally generated DCLKP/M** output (derived from CLKP/CLKM) for syncing the FPGA receiver?
3. Are there any register configurations or startup conditions required to ensure internal DCLK mode is active?
4. Are there any risks or limitations in using the internal DCLK mode?
From Figure 7-3 in the datasheet, it appears that DCLKIN is not necessary for generating the DCLKP output, but I would appreciate official confirmation and recommendations.
Thank you for your support!
