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ADC128S102QML-SP: Rise/Fall time constraints, Digital input hysteresis, and VD/VA power configuration concerns

Part Number: ADC128S102QML-SP
Other Parts Discussed in Thread: ADC128S102

Tool/software:

I'd like to find out if there is a maximum rise/fall time for the digital inputs. For a 16MHz sinusoidal clock, the 20/80 rise time would be about 12.8ns, so I'd estimate that would at least be under or equal to the maximum rise/fall time. Also, is there any amount of hysteresis in in the chip select and SCLK inputs? That would help with slow edges.

On another note, the Typical Application has VD power connected through a series 51 Ohm resistor, which seems like a poor design choice. Perhaps the VD and VA pins are swapped, and VA is intended to be after the 51 Ohm series resistor, with VD connected directly to the 3.3V supply, especially considering the analog inputs and AGND are on the left side of the chip and the digital signals and DGND are on the right side. It seems absurd to apply VD through a 51 Ohms series resistor considering DOUT is driving a 50 Ohm characteristic impedance trace and will source 30 or 40mA into that capacitive load when charging it.

I suspect this sentence pertains only to VA and not to VD, "Due to the low power requirements of the ADC128S102, it is also possible to use a precision reference as a power supply." That just sounds crazy if that's intended to include VA and VD!

  • Hi Mark,

    I'll try to address all of your points in this reply. Let me know if I miss something.

    For a 16MHz sinusoidal clock, the 20/80 rise time would be about 12.8ns, so I'd estimate that would at least be under or equal to the maximum rise/fall time. Also, is there any amount of hysteresis in in the chip select and SCLK inputs? That would help with slow edges.

    Here, are you considering using a sine wave as a clock, relying on some hysteresis to help out? Are you just using it for the analysis of the rise and fall times based on the maximum SCLK frequency spec? The digital inputs do not have any integrated hysteresis/Schmitt triggers, so this will need to be externally implemented if necessary.

    Otherwise, rise and fall times have not been characterized to this device, but they are forgiving. I haven't yet experienced a case where the rise and fall times have posed an issue in a customer's system, nor have I heard of such a case from anyone else, so in general, I would say it's not much of a concern. As a general rule of thumb, I recommend keeping rise and fall times between 6ns and 15ns for good edge detection, to prevent signal ringing, and for good EMI performance. Let me know if your controller can fulfill those timings. 

    The idea behind the 51 ohm resistor there is to give VD an RC time constant so it ramps up after VA. This is to ensure the VD < VA + 0.3 power on requirement, as VA should ramp up before VD. This requirement is due to an internal diode going from VD to VA. Naturally, VD will then ramp down slower than VA, but as long as the diode is not biased, or current is sufficiently limited, this will not cause any damage or long-term reliability issues.

    DOUT does not necessarily require a 50 ohm impedance trace in SPI. Some series resistance is usually added to limit the rise and fall times and prevent overshoot/ringing.

    The bulk of the current is not provided by the supply, in this case a precision voltage reference, but by the decoupling capacitors. It only has to provide the full current if the capacitors are fully discharged on power up, and what is required to replenish the charge on them. Because of that, it's a good idea to have larger bulk decoupling capacitor, and a smaller decoupling capacitor close to the supply pins. The digital supply actually draws relatively little current in comparison to the analog supply.

    Regards,
    Joel

  • So basically you're telling me the ESD protection circuit design is messed up since every pin has ESD diodes to VA rather than having the digital signal pins to VD, and you had to compromise the VD power supply to accommodate the design flaw. It's funny how analog design engineers always talk about noisy digital signals in their datasheets, but then design boards that created that digital noise. Adding series 100 Ohm resistors to the DOUT is simply a band aide that marginalizes the read data timing back at the controller. The DOUT driver output impedance is already relatively high, the fast corning being over 50 Ohms, so adding more series resistance at the driver will simply result in a very slow, stairstep signal impairment at the controller's input pin that will nearly always be somewhat non-monotonic.

    50 Ohm traces may not be required, but they are prevalent everywhere, so your chip should be capable of driving them with adequate signal integrity. I know the edges on DOUT aren't generally important with respect to monotonicity, but it's better to not do it on purpose.

    I'm working with the radiation hardened part, so these issues are critical to the design. The datasheet stating that "it is possible" to use a voltage reference to power it simply compromises the analysis, especially when no specific requirements for the voltage reference design.

  • HI Mark,

    I don't necessarily disagree with any of your points. The power supply sequencing requirement is something we have eliminated with our newer devices with better design.  For some history, the original commercial device was released in 2005 by National Semiconductor, and we inherited it as part of its acquisition. The rad-hard version has a lot of flight heritage and history to put it briefly. 

    What I would like to figure out is if I can run any tests or contact anyone to quell some of your concerns with this device. We can talk more in depth via email if you would prefer to get into the minutia. I've sent a friend request your way if you want to message/email me directly, or I can email you directly if that's okay. 

    Regards,
    Joel