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ADC3543: ADC3543 DDR Complex Mode Configuration

SooHwan Kim
Prodigy 10 points
Part Number: ADC3543
Other Parts Discussed in Thread: ADC3643

Tool/software:

I'm developing a custom adc3543 board, which is required to have 18bit complex decimation-4 interface at 61.44 Msps. 

3 questions I have.

1. In adc35xx EVM GUI,  I can't set up ddr mode with complex interface for adc3543. 

   According to specsheet, It should be possible. Does adc3543 support ddr complex interface?

                 

2. adc3543 specsheet seems to be imcomplete. there's no information about 16bit or 18bit ddr complex mode.

    Figure8-44 shows only 14bit ddr real mode.  How can I configure output bit mapping for 18bit complex mode?

    

   Additionally, Regarding to Table 8-20, It looks like supporting only 14bit ddr real output.

                 

3. provide me with a reference register settings. In EVN GUI, can't get any data. It may be my side problem. 

   It will be helpful to resolve my issues.

Best Regards

SooHwan Kim

  • 0
    TI__Mastermind 40050 points

    Hi SooHwan,

    Let me work on this for you. Please give me a few days to respond.

    Could you tell me your exact features would like the setup the part?

    ADC3543

    14b

    DDR

    Complex Decimation

    Decimation by ?

    sampling rate?

    anything else?

    Please advise so I can better provide some guidance here.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 10 points

    OK. I'll wait for you reply.

    ADC3543, 16 or 18 bit DDR Complex Decimation by 4, Sampling Rate is 61.44MHz.

  • 0 in reply to SooHwan Kim
    TI__Mastermind 40050 points

    Hi SooHwan,

    Thank you for the details. Let me look into this for you.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 40050 points

    Hi SooHwan,

    Thank you for your patience. I have had some setup issues myself for this ADC in the lab.

    I will resume this on Monday and hopefully give you a config file that will work for your setup.

    One note, you cannot use DDR mode when in Complex decimation. You need to use 2wire mode.

    I will config the ADC that way moving forward.

    I will update you on Monday by the EOD.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 40050 points

    Hi SooHwan,

    I was able to set this up on the lab bench today.

    Please see attached configuration file for the ADC and see if this works for you.

    Regards,

    Rob

    Fullscreen ADC3543_2W_Decby4-Complex.txt Download 
    0x7	0x2b
0x8	0x0
0x9	0x0
0xd	0x0
0xe	0x0
0x11	0x0
0x13	0x0
0x14	0x0
0x15	0x0
0x16	0x0
0x19	0x82
0x1a	0x0
0x1b	0x10
0x1e	0x0
0x20	0x0
0x21	0xe0
0x22	0xf
0x24	0x7
0x25	0x20
0x26	0x88
0x27	0x10
0x2a	0x55
0x2b	0x55
0x2c	0xd5
0x2d	0x28
0x2e	0x10
0x31	0x55
0x32	0x55
0x33	0xd5
0x34	0x28
0x39	0x4c
0x3a	0x0
0x3b	0x54
0x3c	0x4e
0x3d	0x5c
0x3e	0x56
0x3f	0x64
0x40	0x5e
0x41	0x6c
0x42	0x66
0x43	0x0
0x44	0xc
0x45	0xe
0x46	0x14
0x47	0x16
0x48	0x1c
0x49	0x1e
0x4a	0x24
0x4b	0x26
0x4c	0x2c
0x4d	0x4d
0x4e	0x47
0x4f	0x55
0x50	0x4f
0x51	0x5d
0x52	0x57
0x53	0x65
0x54	0x5f
0x55	0x6d
0x56	0x67
0x57	0x0
0x58	0xd
0x59	0xf
0x5a	0x15
0x5b	0x17
0x5c	0x1d
0x5d	0x1f
0x5e	0x25
0x5f	0x27
0x60	0x2d
0x61	0x48
0x62	0x0
0x63	0x50
0x64	0x4a
0x65	0x58
0x66	0x52
0x67	0x60
0x68	0x5a
0x69	0x68
0x6a	0x62
0x6b	0x0
0x6c	0x8
0x6d	0xa
0x6e	0x10
0x6f	0x12
0x70	0x18
0x71	0x1a
0x72	0x20
0x73	0x22
0x74	0x28
0x75	0x49
0x76	0x0
0x77	0x51
0x78	0x4b
0x79	0x59
0x7a	0x53
0x7b	0x61
0x7c	0x5b
0x7d	0x69
0x7e	0x63
0x7f	0x0
0x80	0x9
0x81	0xb
0x82	0x11
0x83	0x13
0x84	0x19
0x85	0x1b
0x86	0x21
0x87	0x23
0x88	0x29
0x8f	0x0
0x92	0x0

  • 0 in reply to Rob Reeder
    TI__Mastermind 40050 points

    Hi SooHwan,

    Please ignore this config file. I found an error on the setup. 

    Please give me a few more days to get the correct config file to you.

    Apologize for the delay.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 10 points

    OMG. If I do as you say, I can't setup complex decimation in parallel cmos interface. 

    It's contradict to adc3543 specsheet. 

    adc3543 specsheet must be updated. 

    I should redesign adc3543 interface. Fortunately, Fpga is used in my design. 

    I'll wait for your 2w-setup. 

  • 0 in reply to SooHwan Kim
    TI__Mastermind 40050 points

    Hi SooHwan, 

    Thank you for pointing this out in the datasheet. 

    In the ADC GUI it does not let me config the device/adc this way. As the option to do so, is disabled.

    I am confirming for design and will let you know.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 10 points

    Hi Rob. 

    How's 2W-setup going?

    I recalculated design parameters and is shown as below:

    Samping Rate (Hz) 61,440,000
    Complex Decimation  16
    Output Resolution 16
    Num of Wries 2
    FCLK (Hz) 3,840,000
    DOUT Rate (Hz) 61,440,000
    DCLKOUT (Hz) 30,720,000
    Bandwidth 3,072,000

    I have no evm and can't set up adc3543 related stuff at adc35xx GUI.

    Please check these parameters and send register files. 

  • 0 in reply to SooHwan Kim
    TI__Mastermind 40050 points

    Hi SooHwan,

    Thank you for your patience.

    I am working with the design team internally on this.

    Seems we need new FW created in order to verify the spi write sequence to setup the ADC correctly.

    I am working on this today and will provide you an update by the end of the day.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 40050 points

    Hi SooHwan,

    Please see attached configuration.

    Let us know if this works for you.

    Regards,

    Rob

    Fullscreen ADC3643_2W_Decby4-Complex-New.txt Download 
    0x0     0x1
0x0     0x1
0x7     0x2b
0x13    0x1
0x13    0x0
0xa     0x7f
0xb     0xee
0xc     0xfc
0x18    0x10
0x19    0x82
0x1b    0x90
0x1f    0x50
0x24    0x6
0x25    0x20
0x27    0x10
0x2e    0x10

  • 0 in reply to Rob Reeder
    Prodigy 10 points

    Is there any reason to reset twice?

    It seems to be cleared automatically. 

    Also 0x2E address is not shown in specsheet. 

  • 0 in reply to SooHwan Kim
    TI__Intellectual 1550 points

    Hi SooHwan,

    No, there is no reason to reset twice. This is a typo. You are correct about register 0x2E. This config was generated for the ADC3643, which is the dual channel version of the ADC3543. Register 0x2E configures the output order of channel B in complex decimation mode. Since you only have one channel, this register write can be omitted.

    Please try this configuration sequence and let us know if it resolves your issue.

    Best,

    Luke Allen

  • 0 in reply to Luke Allen
    Prodigy 10 points

    The setup that you suggest, doesn't work for me. but it helps to analyze the relationships of regs.

    and some requirement is changed as below:

    - sampling rate = 61.44MHz

    - complex deimation = 8

    - nco frequency = 8.56MHz (for 70.0MHz input)

    - 2wire 16bit mode

    - dclk = 61.44MHzz

    Final register setup is as below:

    0x00, 0x01
    0x07, 0x4B
    0x13, 0x01
    0x13, 0x00
    0x08, 0x02
    0x0E, 0x04
    0x0A, 0xFF (same as specsheet)
    0x0B, 0xEF
    0x0C, 0xFC
    0x18, 0x10
    0x19, 0x82
    0x1B, 0x08
    0x1E, 0x30
    0x1F, 0x50
    0x20, 0x00
    0x21, 0xFC
    0x22, 0x0F
    0x24, 0x06
    0x25, 0x31
    0x2A, 0xAB
    0x2B, 0xAA
    0x2C, 0xAA
    0x2D, 0x23
    0x27, 0x10
    0x26, 0xA0
    0x26, 0x80

    and It works!.

    for 70.1MHz input, ILA result is show below:

    Thank you for support.

  • 0 in reply to SooHwan Kim
    TI__Intellectual 1550 points

    Hi SooHwan,

    I'm glad to hear you were able to get it working! I am going to close this post, but if you have any other questions please feel free to start another thread.

    Best,

    Luke Allen