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ADS7067: Auto-sequence SDO Data number of clocks

Part Number: ADS7067

Tool/software:

In the SBASA78B – MARCH 2021 – REVISED SEPTEMBER 2024 datasheet/documentation for the AD7067 the section 6.4.4  Auto-Sequence Mode contains diagram "Figure 6-15. Starting Conversion and Reading Data in Auto-Sequence Mode". In that diagram it shows that DAT AINx arrives on SDO in just 12 clocks. Is this a typo? This is a 16-bit ADC and there is no mention of 12 clock size values anywhere else in the document I suspect this is a mistake and that really 24 clocks worth are being received just like in other modes of operation like on-the-fly and manual mode.


  • Hello Jacob, 

    Thank you for posting on TI's E2E forum! 

    In manual mode the ADS7067 has a latency of N+1, meaning that when the conversion begins the responding data will be output in the N+2 frame (shown in Figure 6-13).

    With auto-sequence mode it is able to cut that down to N+1, once it is fully in auto-sequence mode. To fully enter auto-sequence mode, there is still an initial N+2 latency after SEQ_START has been set to 1b, but the following frames when sequencing through the selected channels will be N+1.

    If the cycle where SEQ_START=1b is N, then the data in cycle N+1 should be ignored (this frame needs a minimum of 12 clocks), and the 1st valid data for the channels in the sequence would be in N+2, the 2nd a cycle after that (N+3), etc. Cycle N should always have 24 clocks, N+1 is a minimum of 12 clocks, and cycles after that should correspond to the configured output data frame size.

    Best regards, 

    Yolanda