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AFE7900EVM: AFE7900 EVM Link with ZCU102

Henry Yuh
Prodigy 10 points
Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900, , AFE7950, AFE7950EVM

Tool/software:

We have an AFE7900 EVA board and put it on our Xilinx ZCU102 FPGA Board, TI FAE give us a demo zip file which was demo in another customer. We import this demo file into Xilinx Vitis,  rebuild it and run it, it works fine, no error shown in UART log.

We could only see the C code in Vitis, and can not see any hardware code . So, we try to rebuild the hardware code of FPGA by ourselves, and run the same C code. But we got some UART log errors as attached file: AFE7900EVA+Zcu102_err.png

Our hardware block diagram is shown as attached file:  ZCU102_PL_Block_Diagram.png.

Would you please check what’s wrong there.

  • 0
    TI__Genius 17831 points

    Hi Henry,

    Was there any change to the bringup file? Can you confirm that you are using an AFE7900EVM? The readcheck that is failing, in line 9, is used to check between the AFE7900 and AFE7950 and it is failing and reports the chip version of the AFE7950. 

    If you are using an AFE7950EVM then you would need to generate a new log specifically for the AFE7950 and this issue would solve.

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 10 points

    Hi, David, 

     Thanks for your reply, You are right, we used ZCU102 Link with AFE7950EVM, and got this error。 Would you please advise how to generate a new log specifically for the AFE7950? Using Latte ? 

    Later, we got AFE7900EVM and tried the same way. It showed another error message. Please see the following.

     

    Would you please advise what’s wrong there.

  • 0 in reply to Henry Yuh
    TI__Genius 17831 points

    Hi Henry,

    To generate a log for the AFE7900EVM you can open the Latte software with no EVM connected and follow the normal bringup procedure. This will put the SW in simulation mode and then you can run the script to generate a configuration file, following section 9 of the app note linked below. 

    https://www.ti.com/lit/ug/sbau412a/sbau412a.pdf 

    In regard to the errors you are seeing, can you confirm that the Master_reset_n and tx_sync_resets were both taken out of reset before programming the AFE? 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 10 points

    Hi, David, 

    We  got a AFE7900 EVA board a couple days ago, while we rebuild the Xilinx project with the original files  provided by TI (.including xsa, and C file) ,  it was available to run demo with ZCU102,  But we could not rebuild the same hard ware file with the JESD_204C IP provided by TI. 

    We have tried to rebuild the Xilinx hardware follow the instructions of  "the AFE79xx SPI Bringup Guide With Xilinx FPGAs", but it is fail to demo with ZCU102.

    Would you please advise how to config your  JESD_204C IP and rebuild the Hardware file (xsa) , Should we change the mapping order of sedes lane pin? 

    or Would you please provide the detail step to rebuild the Xilinx hardware for the demo with ZCU102. 

    -Henry-