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AFE7950EVM: configure LMK04828 in AFE7950EVM

Part Number: AFE7950EVM
Other Parts Discussed in Thread: LMK04828

Tool/software:

Hello,

i need to change the configuration for this device but don't see a easy way to do it with the tools you provide.

I have access to all the docs and software via a colleague that have access to the repository in your website and I think I have everything.

I have a xilinx evm kcu105 and im using the reference designs for this board and follow the guide you provide to configure the boards and test the AFE7950EVM.

following the TI204c-setup.docx inside the repo

the only info i found for configuring the LMK04828 is in page 3:

after launch Latte. Run setup.py and devInit.py respectively.

  1. Configure LMK04828 clocking device on AFE EVM

Run TI_IP_10Gbps_8Lane_ConfigLmk.py.

I want to change the clocks used in the LMK04828 to achieve another sample rates.

so i need to configure the LMK04828 via this script

there is any place where is defined and explained the API used for this script?.

Regards.

  • Hi Juli,

    My recommendation would be to reference the 'AFE79xx_Configuration_Parameters' document which is available in the secure folder.

    Is there a specific sample rate you would like to use? If so then i can provide an example for that rate. 

    Regards,

    David Chaparro 

  • thanks for answer David,

    yes I want to modify the sampling rates to something maybe is not feasible with the internal reference of 122,88MHz used to feed all the clocks in the EVM and JESD interface.

    I want to use a sampling rate in the FPGA about 64Msps.

    just discover there is another example who use an external reference (TI_IP_5Gbps_2lanes_4Rx_ConfigLmk.py)  and would like to see if this can solve our requirements.

    the parameters used for this example:

    lmkParams.pllEn = False

    lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False

    lmkParams.lmkFrefClk = True

    setupParams.fpgaRefClk = 61.44

    this example use a sampling rate of 2949.12MSPS and a ddcFactorRx of 48 so my sampling rate in the FPGA is 61,44MSPS.

    what should I configure in this example to achieve the 64Msps?.

    I have tried to feed the EVM with external reference of 1024MHz and the example seems working correctly but if I configure the parameters in the scripts according the real values gives me errors of not compatible values of internal VCO frequencies in range so not sure if I'm doing it correctly.

    Also after that I need to enable the tx channel with twice the sampling rate and a ducfactor of 48 to achieve a sampling rate of the FPGA of 128MSPS but I see the configuration of this example is not correct. so I guess i have to change more parameters to achieve this.

    the example have the next parameters for the transmitter:

    sysParams.Fdac = 2949.12*3

    sysParams.txEnable = [False,False,False,False]

    sysParams.ducFactorTx = [18]*4 #DUC interpolation factor for TX A, B, C and D

    sysParams.jesdTxProtocol= [0,0]

    sysParams.jesdTxLaneMux = [5,1,2,3,0,4,6,7]

    sysParams.LMFSHdTx = ["44210","44210","44210","44210"]

    as far I can understand these parameters seems not suitable for 2 lanes and 5gbps, at least tried to only enable the TX part in the script and FPGA and is not working (with errors in the JESD link).

    the only changes I made in the FPGA project is change the parameter IP_TYPE to "RXTX". the others parameters were configured as:

    NUMBER_OF_RX_LANES 2
    NUMBER_OF_TX_LANES 2

    LANE_ADC_TO_GT_MAP {0,1}

    LANE_DAC_TO_GT_MAP {0,1}

    RX_LANE_POLARITY 2'b11

    TX_LANE_POLARITY 2'b11

    Some guidelines or maybe the correct parameters for my goal would be much appreciated.

    Thanks

  • Hi Juli,

    If you can fill out the table below i can create a custom script for you.

    TX

     

    # of TX enabled

    ?

    Fs DAC [GSPS]

    ?

    Single or Dual Band

    ?

    Interpolation

    ?

    FB

     

    # of FB enabled

    ?

    Fs ADC[GSPS]

    ?

    Single or Dual Band

    ?

    Decimation

    ?

    RX

     

    # of RX enabled

    ?

    Fs ADC[GSPS]

    ?

    Single or Dual Band

    ?

    Decimation

    ?

    JESD

     

    Encoding (If not sure we can pick for you)

    ?

    Available Lanes on FPGA

    ?

    Max Lane Rate Supported by FPGA [Gbps]

    ?

    Deterministic Latency and/or Multi-Chip Synchronization Required (Y/N) (Note for multi-chip synchronization DC couple SYSREF is recommended)

    ?

    Clocking

     

    Use AFE internal PLL

    ?

    Regards,

    David Chaparro