Tool/software:
Hi,
I am dealing with SYSREF capture circuit, section 7.3.10 of datasheet.
I am not sure which clock is the 'device clock' in my design.
The only input clock I have is DACCLK with a frequency of 2534.4 GHz. It is used directly as DAC sample clock, i.e. I am not using the internal PLL of the chip.
Is this clock the 'device clock' referred to in section 7.3.10? Or is it other clock internally generated from that one?
This image shows the clocking configuration I am using:
Best Regards,
Miguel
