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ADS131A04: ADS131A04

Part Number: ADS131A04

Tool/software:

I have 3 daisy-chain ADCs ADS131A04, where I want to read data from all the 4 channels of each:

1) Does the order of configured registers (WREG and RREG) matters?

2) DO I need to configure the D_SYS_CFG register? ( I only configured A_SYS_CFG, CLK1, CLK2 and ADC_ENA)

3) I had my design working on a development board, but when I wanted to implement the same design on another board with a difference only of a galvanic isolation I am not capturing data anymore

4) How to trigger the ADCs in the initialisation? 

  • Hi Imene Smida,

    Welcome to the E2E forum.

    1. No.

    2. It is not necessary to configure D_SYS_CFG register if you want to use the default settings in this register.

    3. It is hard to say what caused the issue without more information including the schematic and timing. You could test one signal ADC without or with galvanic isolation first, then test all 3 ADC devices. You can also reduce the SCLK frequency to see if there is any improvement.

    4. Can you clarify what the meaning of the "trigger" is?

    BR,

    Dale

  • for the question 4) how do the ADCs start working in the initialisation phase ?

  • Hi Imene Smida,

    Please see the procedure below:

    • After the ADC is powered up, firstly your will have to send an UNLOCK command to enable the interface and begin communicating with the device.
    • After being unlocked from POR or after reset, the device enters a low-power standby mode with all ADC channels powered down by default, so you will have to enable the channels in ADC_ENA register, then select a proper voltage reference source in A_SYS_CFG register, the external voltage reference is selected by default.
    • Finally, sending the WAKEUP command brings the device out of the standby mode and start conversions.

    BR,

    Dale

  • Should we reset the ADCs in the init state ?
    Thank you 

    BR 

    Imene

  • Hi Imene,

    A RESET can put the device to a default and known state, this is a good practice before configure the registers and start conversion.

    BR,

    Dale

  • Hi Dale 

    I am getting 0xff04 in the 3 ADCs and ffff in the 12 channels, how can that be fixed 

    BR

  • Hi Imene,

    It is hard to say the reason without any information. Can you provide your timing plot for SPI signals and /DRDY together?  a timing captured with a logic analyzer will be good to check. Can you get correct conversion data or register data with just one ADC? if not, I would suggest you to test and debug one ADC unit first.

    BR,

    Dale