ADS7066: Issues with Channel Measurements

Hello Jon, 

Thank you for posting on TI's E2E Forum! 

500µs is quite substantial, so I would like to understand more how the ADS7066 is being used and configured to make a better assessment, if you could please answer some follow up questions:

• Could share a schematic of the ADS7066 in your system? or are you using an EVM? 
• What kind of input are the channels seeing? is it a DC input?
  • What is the expected code when you read back and what are you actually reading back? 
• What sampling frequency are you using? 
• is the 500µs needed for all channels or just a few? is it needed always or only when switching channels?
• What does your "SPI_ADS7066_sendNOP(hADS7066)" function look like?
  • This is mainly to confirm N+2 latency is being accounted for. 
• It seems like the ADC is configured in Manual Mode, could you confirm, or what mode is the ADC in? 
• Is the ADS7066 using it's internal reference or is there an external reference? 

You thoughts on the ADS7066 internal S/H circuit being able to make stable readings in the sub-µs range is correct, as well as it is a good practice to allow some time for the mux/switch settling.   

Without knowing the full system it is difficult to make an assessment, but here are some initial debugging steps to start with:

1. What is the voltage at the REF pin? Is the voltage stable or is the reference voltage noisy? 
2. When reading data is the correct latency being taken into account depending on the configured mode (section 7.4)?
   1. For example, in Manual Mode (7.4.2) in figure 7-13 it shows how the frame where the channel is selected as Cycle N, then in Cycle N+1 the mux changes the channel to the selected and data is acquired, and finally on Cycle N+2 the data is converted and output on SDO
   2. 
3. If you continue reading out data (same channel) without the 500µs delay does the data out eventually become stable or does it remain unstable throughout?
   1. Follow up if the latter: does your readback function include a write to select channel configuring the mux every time?  or is it just a NOP(s) + readback?

Best regards, 

Yolanda

Hi Yolanda, 

Thanks for the replay.

• Could share a schematic of the ADS7066 in your system? or are you using an EVM?
  • Find attached the schematics.

• What kind of input are the channels seeing? is it a DC input?
  • Now I am doing test with a DC input of a power supply of 5 V or 3 V 
  • What is the expected code when you read back and what are you actually reading back? 
  • I expect to read an input voltage of 5 V or 3 V from the ADC. The communication between the ADC and the MCU is functioning correctly; however, the issue lies with the data sent by the ADC. The ADC readings are not accurate.
• What sampling frequency are you using? 
  • The SPI CLK is set at 1 MHz.
• is the 500µs needed for all channels or just a few? is it needed always or only when switching channels?

  • I need a consistent 500 µs delay every time I read a channel. Note that the ADC output is always stable when performing the 5 V read; however, instability occurs specifically during the 3 V read.

• What does your "SPI_ADS7066_sendNOP(hADS7066)" function look like?
  • This is mainly to confirm N+2 latency is being accounted for. 

void
SPI_ADS7066_sendNOP(HANDLER hADS7066){
    PSPI_ADS7066DESC pADS7066Desc = (PSPI_ADS7066DESC)hADS7066;

    uint8_t dataTx[4] = { 0 };
    uint8_t numberOfBytes = SPI_CRC_ENABLED(pADS7066Desc) ? 4 : 3;
    EMBL_RETCODES ret = EMBL_OK;

    dataTx[0] = OPCODE_NULL;
    dataTx[1] = OPCODE_NULL;
    dataTx[2] = OPCODE_NULL;

    if (SPI_CRC_ENABLED(pADS7066Desc)) { dataTx[3] = SPI_ADS7066_calculateCRC(&dataTx[0], 3, 0xFF); }
    do {
        ret = WRSPI_Transmit(pADS7066Desc->hSPI, dataTx, numberOfBytes);
    } while (ret == EMBL_BUSY);
}

where : #define OPCODE_NULL ((uint8_t) 0x00)

• It seems like the ADC is configured in Manual Mode, could you confirm, or what mode is the ADC in? 
  • Yes, is in Manual Mode.
• Is the ADS7066 using its internal reference or is there an external reference? 
  • External reference of 5 V

Find attached the Init that I perform to the ADC:

void
SPI_ADS7066_basicInitObject(HANDLER hADS7066) {

    if (CHECK_MEMORY(hADS7066)) {
        Throw(EMBL_WRONGPARAMS);
    }

    // Force all channels to be analog inputs (voltage from sensors)
    // No CRC

    SPI_ADS7066_writeSingleRegister(hADS7066, GENERAL_CFG_ADDRESS, OPMODE_CFG_CLK_DIV_6);
    if (SPI_ADS7066_readSingleRegister(hADS7066, GENERAL_CFG_ADDRESS) != OPMODE_CFG_CLK_DIV_6)
    {
        Throw(EMBL_ERROR);
    }

    // Normal operation for output data, 4-bit channel ID appended to ADC data
    // SPI mode 0

    SPI_ADS7066_writeSingleRegister(hADS7066, DATA_CFG_ADDRESS, DATA_CFG_APPEND_STATUS_FOUR_BIT_CHID);
    if (SPI_ADS7066_readSingleRegister(hADS7066, DATA_CFG_ADDRESS) != DATA_CFG_APPEND_STATUS_FOUR_BIT_CHID)
    {
        Throw(EMBL_ERROR);
    }

    SPI_ADS7066_writeSingleRegister(hADS7066, OSR_CFG_ADDRESS, OSR_CFG_OSR_16);
    if (SPI_ADS7066_readSingleRegister(hADS7066, OSR_CFG_ADDRESS) != OSR_CFG_OSR_16)
    {
        Throw(EMBL_ERROR);
    }

    // High speed oscillator enabled

    SPI_ADS7066_writeSingleRegister(hADS7066, OPMODE_CFG_ADDRESS, OPMODE_CFG_CLK_DIV_10);
    if (SPI_ADS7066_readSingleRegister(hADS7066, OPMODE_CFG_ADDRESS) != OPMODE_CFG_CLK_DIV_10)
    {
        Throw(EMBL_ERROR);
    }

    // Set the sequence mode to manual, we have to select the channel mannually

    SPI_ADS7066_writeSingleRegister(hADS7066, SEQUENCE_CFG_ADDRESS, SEQUENCE_CFG_SEQ_MODE_MANUAL);
    if (SPI_ADS7066_readSingleRegister(hADS7066, SEQUENCE_CFG_ADDRESS) != SEQUENCE_CFG_SEQ_MODE_MANUAL)
    {
        Throw(EMBL_ERROR);
    }
}

Without knowing the full system it is difficult to make an assessment, but here are some initial debugging steps to start with:

1. What is the voltage at the REF pin? Is the voltage stable or is the reference voltage noisy? 
   1. The VRef voltage is a 5 V stable voltage. 
2. When reading data is the correct latency being taken into account depending on the configured mode (section 7.4)?
   1. For example, in Manual Mode (7.4.2) in figure 7-13 it shows how the frame where the channel is selected as Cycle N, then in Cycle N+1 the mux changes the channel to the selected and data is acquired, and finally on Cycle N+2 the data is converted and output on SDO

   2. The cycle is executed correctly. First, I change the MUX OUT (Cycle 1), then I send the NOP condition (Cycle 2) to ensure the MUX change is performed properly, and finally, I read the data (Cycle 3). A total of 3 cycles are involved.

3. If you continue reading out data (same channel) without the 500µs delay does the data out eventually become stable or does it remain unstable throughout?

   1. I am reading only one channel, but the measured voltage is unstable, even though the input is a steady 3.00 V.

4. 
   1. Follow up if the latter: does your readback function include a write to select channel configuring the mux every time?  or is it just a NOP(s) + readback?
      1. I write to select the channel, send the NOP condition, and then perform a readback. 

Best regards, 

Jon.

Hello Jon, 

Thank you for the thorough response. 

Could you share the impedance of the input sources? both the 3V and 5V. Is there anything driving these sources? or is it a direct measurement? 

Would you be able to share how the 3V input signal looks like at the ADC input when these measurements are happening? 

Or could you observe how it looks at the input of the ADC during the 500us delay to see if there is any noticeable glitch and/or an exponential voltage recovery (like a capacitor charging) when the ADC is measuring?

Best regards, 

Yolanda

Hi Yolanda, 

The input source for the ADC is directly connected to the device’s power supply via some cables. The part numbers for the regulators are:

• BD33GA3WEFJ for the 3 V supply

• TR10S05 for the 5 V supply

Please note that we did not include a charge-kickback filter at the ADC input.

Attached, you’ll find the measurement of the ADC input during the 500 µs delay. As observed, there are no noticeable glitches or voltage recovery in the signal.

Best regards, 

Jon.

Thanks again Jon, 

This is very interesting, 500us is not an expected delay, especially at a 1MHz sclk. 

The output of the BD33GA3WEFJ does seem stable and judging from the datasheet it should be able to provide the current needed to drive the ADC on its own at 1MHz. I

Is there any substantial noise on the 5V source at AVDD or REF pins? 

Being that the 5V input (same as supply/reference) did not see the issue I would like to confirm that there is a similar reference for the ADC, 5V source, and the 3V source. They all share the same ground, or they are tied together at some point, correct? 

Could you also be able to share an oscilloscope or logic analyzer picture of the data communication (SCLK, CS, SDO, SDI)?   

Best regards, 

Yolanda