Tool/software:
Environment
I'm working on an ESP32-S3 project. I'm communicating with an ADS8688 using the HSPI which operates in Mode 1 (sample on SCK falling edge) at 1MHz.
I use the esp-idf framework (4.4.7) to setup the bus, device and run half-duplex transmissions with DMA.
Problem
After much head scratching I've discovered what I believe to be a delay between SCK falling and MISO being sampled. I've proven this by scoping the transfer, and noting what the ADC is outputting with 0V applied (approx 0x8000, the mid point of my ADC counts) vs what is sampled (approx 0xFFFF or 0x0000).
See below reading, where what I should be sampling is 0x7FF6 (something close to 0x8000) but what I actually get is 0xFF60 (something close to full scale). 
Similar is true if it measures just north of the mid point (0x8005), I then get 0x0050.
I've ascertained that a delay in sampling at the MCU would cause this, leading to left shifting the whole thing. From 'scoping it I can see MISO holds for a max of 17ns after the SCK falling, hence my concern.
Here's a signal transition (BE: SCK, YW:MISO) in case you were wondering about ringing:
Things I've Tried
- Increasing the SCK - concerningly I get closer to what I expect at 15MHz vs 1MHz.
- Adding capacitance to slow the signal & use mode 0 - this is in fact how it was (incorrectly) working previously. Again proving what I'm experiencing acquiring the correct MISO bit. This, however, is what I would call a bodge.
Question
Is this a problem you've encountered before in implementation? What can I do to resolve it? I considered adding a buffer or latch to delay/hold the MISO state for a bit (10-50ns) longer, is that common practice?
Thanks
