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AFE5808A: Consultation on circuit design questions of AFE5808A/AFE5807

ken chen
Intellectual 330 points
Part Number: AFE5808A
Other Parts Discussed in Thread: AFE5807, AFE5808, AFE5807EVM, AFE5805, AFE5828

Tool/software:

Hi TI Team，

The following are some doubts about the customer's application selection of afe5808/afe5807. Please help give some suggestions for selection.

I'm currently selecting afe5808/afe5807 here. My requirement is that the echo signal of the transducer is ±400mV with a frequency of 1Mhz.

Problem point 1: During the simulation, it was found that when the input signal is greater than 320mV. Distortion may occur in the output signal. VCNTLP-VCNTLM=0.88V. As shown in the following figure. Even if the voltage of VCNTLP-VCNTLM is increased, distortion will still exist. How does this need to modify the parameters of the circuit?

Question Point 2: If I don't use the CW function, all 8 channels are sent and received separately. Does this mean that DCLKM and DCLKP are not necessary? Just connect the FCLKM and FCLKMP clocks to the FPGA.

Question Point 3: Besides the AFE5808EVM/AFE5807EVM circuit design, are there any other reference designs that can be provided to help?

Question Point 4: Considering the cost issue, does the AFE5805 also meet my requirements? Thank you!

  • 0
    TI__Expert 6965 points

    Hi,

    Q1 : This might be due to LNA getting saturated . Can you change the gain of LNA to 12dB and chceck ?

    Q2 : DCLKP/M is must . This is nothing to do with CW. On each DCLK one bit of each channel will come on respective LVDS lane . So DCLK is must . FCLK will determine the boundary of the sample . 

    Q3 : There is no other reference design which we can share with customers 

    Q4 : We have 16 channel parts like AFE5828. Please look at this also as it gives higher integration of channels.

  • 0 in reply to Sachin H K
    Intellectual 330 points

    Hi Sachin，

    The customer is asking how to change the gain of the LNA to 12dB?

    thanks.

  • 0 in reply to ken chen
    TI__Expert 6965 points

    CHx_LNA_GAIN_0 AND CHx_LNA_GAIN_1 pins are used to control gain.

    Datasheet register mapping is as below . So I expect pin control also will follow the same .

  • 0 in reply to Sachin H K
    Prodigy 10 points

    Hi Sachin，

    I want to know whether the spi interface of afe5808 is connected to 1.8V or 3.3V I/O.

    Theoretically, the SPI、PDN_ADC 、PDN_VCA 、PDN_GLOBAL should be connected to 3.3V I/O, right?

    However, on page 67 of the data manual, I saw that the SPI of the adc was connected to 1.8V, which confused me a lot.

    Hope to get your help,Thank you.

  • 0 in reply to yuewang xie
    TI__Expert 6965 points

    Yes, It can be connected to 3.3VI/O .

    In page 67 , What this mentions is internal spi block is running on 1.8V supply . You can think as 3.3V input level is level shifted to 1.8V in the device and used subsequently.