Tool/software:
Hi,
I am working on a design where the LVDS clocks from the ADC12DL3200 are used as input a PLL inside the receiving FPGA.
We would like to program different user patterns into the ADC (i.e. modify the `UpatX` registers). However, the datasheet says that these should only be modified when LVDS_EN = 0, which means the LVDS clock outputs get disabled/PLL locks get lost/... Is there any way to program different patterns into the ADC while leaving the LVDS clock running?
What happens when "LVDS_EN must be 0" is ignored? Does this simply cause temporary glitching on the output, or is there no guarantee that the programmed pattern will ever be properly output?
Thank you very much.
