Tool/software:
Hello,
I would like to interface the ADS7047 ADC to my FPGA over SPI. I went through the specification in the datasheet. It states that the SPI clock (SCLK) must have a maximum 45/55 duty cycle (tph_CK and tpl_CK)
Is the 45/55 duty cycle (min and max) defined as a percentage regardless of the SPI clock frequency? Or is it an absolute timing in nanoseconds?
My SPI master clock also has a 45/55 duty cycle limit. So I am wondering whether there is a reason for the percentage.
Thank you in advance