ADS9228: Is Data to be match with clock for ADS9228

Dr Marimuthu G

Part Number: ADS9228

Tool/software:

Hello Team,

I am using ADS9228RHAR in our project. let me explain anyone, Is data to be match with respect clock? if yes which clock need to consider.? Please refer the datasheet Page 12. Here i added image for your reference.

From ADC to FPGA 100E impedance connected. Please refer schematic image. So, data signals are pink color and SMPL_CLK clock is Yellow and FCLK is orange. As of now Data is match with SMPL_CLK. is it right or is i need to match FCLK with respect to SMPL_CLK. Can anyone explain?

ADC separated Analog and Digital groun used.

5 months ago

0 Yolanda Gonzalez 5 months ago

TI__Expert 4240 points

Hello Dr. Marimuthu,

Thank you for posting on TI's E2E Forum!

Yes, the data matches the clocks, when synchronizing the data readback the FCLK shows the start of the data output. But it is related the the other clocks as follows:

SMPL_CLK: Sampling Clock (input), the FALLING EDGE of this clock starts the conversion

FCLKP/M: Frame Clock (output), the RISING EDGE of this clock designates the start of the data output on DOUT beginning with MSB.

DCLKP/M: Data Clock (output), the amount of periods of this clock in 1 cycle depends on the lanes and modes configured.

SMPL_CLK starts conversion, but the data readout for that conversion will have some latency of ~2 x t_{SMPL_CLK}as shown on Figure 6-8 (page 14) when in 24-bit data frame. This means that the data from the conversion started on Cycle N, will not be output until the Rising Edge of FCLK in Cycle N+2.