Tool/software:
While the end target is using an ADC12QJ1600EVM this is really about the TI204C-IP.
I apologize for this very basic question, but I am not well versed in JESD204 or Xilinx Vivado.
I am merely trying to the TI204C-IP reference design for the Xilinx ZCU102 board (zcu102_8b10b) to work.
The problem is that when I program the board via Vivado(2023.1) Hardware Manager it says there are no debug cores and the ILA and VIO blocks do not appear anywhere. All that is available are 2 sysmon temperature blocks.
My process has been:
1. Download the TI204C-IP v1.12 and unzip it.
2. Create a new Vivado 2023.1 project adding all the source rtl, Xilinx IP blocks, constraint file, and the 2022 and newer TI-204c_CoreIP.
3. Update all the Xilinx IP.
4. Synthesize the design.
5. Implement the design
6. Create bitstream
7. Open hardware manager, connect to board and program device with the default .bit and .ltx files.
Hardware manager specifically mentions that "no debug cores" are in the design and no ILA or VIO blocks show up.
Without the VIO block, master_reset_n is held low thus keeping the entire design in reset.
What am I missing?
