ADC12QJ1600: ADC12QJ1600

Hi Giora,

Can you please give us more context? The attached PDF doesn't really say much.

So you are over-ranging the analog inputs of the ADC and your JESD link is lost during this time?

Also, what analog input frequency range are you are using?

What is the JMODE being used and sampling rate?

Thx,

Rob

Hello Rob,

As for your questions:

- Yes we over range the ADC inputs.

- Yes the JESD link is lost during this time and stay like this after lowering the signal input.

   We have four signal inputs that are phase aligned ( using sysref ) during saturation one of the channels

   is going out of phase from the three other signals.

- We use JMODE 8 64/66b.

- The BW is ~ 80MHz ( driving the ADC from LMH34201 through 10 ohm resistor and 47pf capacitor on the ADC inputs.

- The signal at ADC input is a pulse ~ 10ns width at half the amplitude with ~ 7ns rise and fall time at 10Khz rate.

- Sampling clock is 1Ghz. Input clock to the ADC is 125Mhz diff Clock OSC.

Regards,

Giora

Hi Giora,

Closing this post and moving it offline.

Please be on the lookout for my email.

Regards,

Rob