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DAC7811EVM: Required Power Supplies

Part Number: DAC7811EVM
Other Parts Discussed in Thread: DAC7811, OPA2277

Tool/software:

Hello,

Can you please clarify what the minimum required power supplies are to operate the DAC7811 EVM? From what I see in the forums, there seems to be some discrepancies between what is printed in the DAC7811 EVM datasheet and the required supply.

My configuration:

Two DAC7811 EVM connected in a daisy-chain. 

The bottom board has W2 in the 2nd slot. The top board has W2 in the 1st slot. 

W3 is connecting 1-2 (the left 2 pins) on both boards.

The switches are set to the left on both boards.

Please note, I am not married to this configuration and if there is a better way to demonstrate a minimal viable product, I would be happy to adjust these settings. At this point, I am just looking to verify my driver code is working. To be clear, my question is, what are the required voltage levels on J3 such that an analog voltage would be visible on J1.4 and J1.6?

Thank you for the assistance,

Ray

  • Hi Ray, 

    If you want to use the on-board references and on board OPA2277 op amps, J3 requires:

    1: VCC - 15V

    2: VSS - -15V

    3: NA

    4: NA

    5: NA

    6: GND

    7: NA

    8: NA

    9: NA

    10: VDD - 2.7V to 5.5V

    Best,

    Katlynne Jones

  • Hello Katlynne, 

    Thank you for the response. I'm continuing to experience issues using the EVM, and I'm hoping you can spot an obvious error. I've connected the power supplies as you indicated. Additionally, I am using the following configuration: 

    Daisy-chain with both EVM's having their switch in the right-position (this is a change from when I initially posted)

    The bottom EVM has W2 in the 2nd spot, the top EVM has W2 in the 1st spot. 

    When reading the SDO (J2T.11) from the top EVM, I can successfully verify that it matches the SDIN (J2B.11) to the bottom EVM. 

    The digital signals are generated by an FPGA PMOD interface with 3.3V logic levels. My SCLK is a relatively slow 20MHz. I can verify all of my signals (SCLK, SYNC, SDIN) are coming out clean with an amplitude near 3.3V as expected. The SDIN signal sent to both DACs is a simple ramp that continuosly cycles from [0,4095]. 

    When I probe the outputs at either J1.4 or J1.6 I am getting -10V constant

    Below is an ILA screenshot that shows the timing of a signal transfer. The first two bits (while SYNC is high) are set to zero. Then, the data sequence is 0000_1100_0111_1000 0000_1100_0111_1000 which uses CTRL = 0000 (for daisy-chaining), and DATA = 3192. Then, the next transfer would be 3193, etc. I expect to see a ramp function at the output of J1.4 and J1.6, but as indicated, I am only seeing a constant. 

    Thank you for any guidance, resolution you can provide.

    Regards,

    Ray

  • Hi Ray, 

    Control bits of all 0 is a no operation function and is used in daisy chain mode when you don't want to update a specific device in the chain. You do want the outputs of both DACs to change so you should be sending 0001_1100_0111_1000 0001_1100_0111_1000. If you only wanted the second device to update you would write 0000_1100_0111_1000 0001_1100_0111_1000 or 0000_xxxx_xxxx_xxxx 0000_1100_0111_1000 where x is a don't care. 

    Try updating this and let me know if you are still running into trouble. If you are still running into trouble, it might be helpful if you can measure the SPI frame on an oscilloscope so I can better review the timings. 

    Best,

    Katlynne Jones

  • Thank you Katlynne,

    Fixing the control registers resolved the issue and I am now seeing the analog signal that I expect.