ADS4222EVM: How to test the ADS4222EVM with a custom connector board

Hi Danidu,

Most of your questions can be address via the EVM user guide.

It is located here: https://www.ti.com/lit/ug/slau333a/slau333a.pdf?ts=1747592891708&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252FADS4222EVM

The ADC EVM simply connects to a TSW1400 (obsoleted) to capture the LVD data.

Regards,

Rob

Hi Rob,

I set up the EVM for Serial Interface (according to Table 1) and DDR LVDS Output (according to Table 5). I am not planning to use the THS4509 Input Op-Amp Configuration and the On-Board CDCE72010 Clock, so those have the default jumper settings.

I provided a 100MHz 0.5Vpp (peak-peak) Sin wave centered around 0V (offset = 0V) for the CLK IN (J19 port), and tested the test patterns for both A and B channels. Here's an image of what I saw for the Ramp and Alternating test patterns.

             

For all ones test pattern, I got 0xffc (1111 1111 1100). For custom test patterns I didnt get the expected output. I got the same results for a 25MHz clock as well.
I generated the clock signal from a signal generator.

This is an image of my GUI configuration,

Any insights on why this is happening and how to fix this and get an accurate output?

Thanks,
Danidu.

Hi Rob,

I measured the voltages at the output pins of the ads4222, when the test pattern was set to All Ones. Here are the values;

DB0_1M = 1.24V
DB0_1P = 0.90V
=> 0_1 bits - 00

DB2_3M = 0.90V
DB2_3P = 1.24V 
=> 2_3 bits - 11

DB4_5M = 0.90V
DB4_5P = 1.24V
=> 4_5 bits - 11 

DB6_7M = 0.90V
DB6_7P = 1.24V
=> 6_7 bits - 11 

DB8_9M = 0.90V
DB8_9P = 1.24V
=> 8_9 bits - 11 

DB10_11M = 0.90V
DB10_11P = 1.24V
=. 10_11bits - 11

I think DB0_1M and DB0_1P voltages are incorrect, that is why I see 0xffc as the output when the test pattern is set to All Ones.  Is my understanding of this correct?

Any clarification on this would be appreciated.

Thanks in advance!

Hi Rob,

I previously made a small mistake in my deserialization logic, but I’ve corrected it now. After the fix, I'm now seeing a much clearer output when testing with the Ramp test pattern. However, I’ve noticed that the 0th and 1st bits consistently remain at 00, and do not change as expected. You can also observe this in the attached image.

To further investigate, I measured the voltage levels at RN9:

• DB0_1M = constant around 1.24V

• DB0_1P = constant around 0.90V

This suggests the 0_1 bits are stuck at 00.

Do you have any idea what could be causing this behavior? I’d really appreciate your help.

Best regards,
Danidu.

Hi Danidu,

Are you capturing the correct format? 2comp or offset binary in the FPGA?

I believe the ADC is offset binary by default.

Regards,

Rob

Hi Rob,

First of all thank you very much for helping me out on this.

When I configure the test pattern to "All Ones," I should see all 12 bits set to '1', regardless of the selected data format (Offset Binary or 2’s Complement) ?
Also when I set the test pattern to "Custom" and input specific values, all bits appear correct except for the 0th and 1st bits, which consistently remain at '0'.

Best,
Danidu.

Hello Rob,

Could you kindly provide some insight into the behavior I'm observing from the EVM? Your thoughts on this would be greatly appreciated.
Looking forward to hearing from you.

Thank you!

Are you setting only 12 bits to the custom pattern or all 14 bits? What is the custom pattern?

Hi Chase,
I realized I had misread the schematic and mistakenly routed only 10 bits from the ADC to the output connector.
    

In the case of the ADS4222, I had assumed that DA0 to DA10 carried the 12-bit output. However, according to the datasheet, the actual 12-bit output spans DA2 to DA13. In my current design, DA12 and DA13 are not connected, which means the two most significant bits (10th and 11th bits) are not being read.

Just wanted to document this in case someone encounters a similar issue.

Despite this, I ran some tests with custom test patterns, and the 10 routed bits appear correct. For instance:

• With a ramp test pattern, the ILA core displays a fairly smooth ramp waveform. (I have attached an image above)

• With custom static patterns, the captured 10 bits match the expected values.

However, for the alternating test pattern, which should toggle between sequences like 1010 1010 1010 and 0101 0101 0101 (as per the datasheet), I instead observe solid values of 1111 1111 1111 and 0000 0000 0000.

Additionally, when I input a sine wave, the captured waveform on the ILA appears highly distorted. I’m unsure whether this is due to:

1. The two missing MSBs, which could be truncating the waveform significantly, or

2. A potential issue in the code I wrote to convert DDR LVDS input into AXI-Stream format.

I also came across this thread on the TI forums where you shared reference code for the Artix-7 FPGA family. I’m not sure if that code would be compatible with my setup, but I’d be grateful for any guidance or clarification you can provide. 
https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1059194/tsw1405evm-replace-the-tsw1405evm-with-artix-7-fpga?tisearch=e2e-sitesearch&keymatch=ADS4222EVM#

Thank you very much in advance!

Hi Chase,

Since I misrouted the two MSBs, I decided to design a new PCB to get the LVDS output from the EVM.
I noticed some confusion in the datasheets. 

According to the ADS4222 datasheet,
pin 57 - CLKOUTP
pin 56 - CLKOUTM

According to the EVM schematics,
pin 57 - ADC_CLKOUT - CLKOUT_M
pin 56 - NO_CONNECT - CLKOUT_P

Appreciate if you can clarify this for me.
Thanks.

Hi Danidu,

The EVM looks to be configurable to a single ended LVCMOS clock through the U12 level shifter OR come as differential from the J8 connector through resistor array RN8. The schematic symbol was likely created with only single ended clock in mind and not redone to indicate differential clock support. I wasn't around at the time but that's what I'd bet on.

I would suggest to drive the clock with differential signal with as large of swing as you can provide, within the ADC operating limits of course.

Thanks, Chase

Hi Chase,
I suppose there's mistake where they have swapped the net names CLKOUT_M and CLKOUT_P in the EVM schematics. I think that's why I got an inverted clock signal in the fpga where the odd bits (D1, D3, D5, ....) are given at the rising edge and the even bits (D0, D2, D4, ....) are given at the falling edge (should be the other way around for LVDS DDR).

I will design a new PCB  to get the output from the J8 connector, I will route all of the lines properly this time.

Can you please explain this. For the alternating test pattern, which should toggle between sequences like 1010 1010 1010 and 0101 0101 0101 (as per the datasheet), I instead observe alternating solid values of 1111 1111 1111 and 0000 0000 0000. I observed this for the first 10 bits. (last two bits are not routed by my mistake, so can't see the output)

For any custom test pattern (like 0xABCD), and for all ones and all zeroes test pattern the 10 bits gave the expected output.
The ramp test pattern also gave a fairly clear output except for some sudden spikes. 
Can you explain why I can't see the proper result for alternating test pattern. 

Thanks very much, really appreciate you helping me out.