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Understanding ADS1278 Frame-Sync signals

Gabriel Calin
Intellectual 300 points
Other Parts Discussed in Thread: ADS1278

Hello everyone,

    I plan to use the ADS1278 on a new project, however I am having some difficulties understanding the Frame-Sync signals described on the datasheet. I would appreciate some help. My questions are:

    - What happens if you generate FSYNC signals with lower period than the conversion rate?

    - What happens if the FSYNC, running exactly at the conversion rate, if slightly out of of phase (from the initial SYNC signal)

    - If you generate the FSYNC signal from a microcontroller that is driven by a different clock source than the ADS1278, even if the timming is very precise and the framing process is synchronized using the SYNC signal, the small crystal drift from both IC will evently result in a alignment drift of FSYNC. It may take some millions/billions conversion cycles or some temperature drift, but it will eventually happens. Is this normal/expected? Is it necessary to issue a new SYNC signal time to time?

Regards,

Calin

  • 0
    TI__Mastermind 43915 points

    Hi Calin,

    The timing diagram is written to explain that the Frame period between FSYNC pulses needs to be 1/Fdata. It needs to be the period of the data rate as it is used to synchronize reading the new conversion results with the microcontroller. If their periods do not match up and FSYNC appears early, I would imagine that you would either read back the same data from the previous conversion or read back all zeroes. I am not completely sure since using this way is out of spec and not something that we test. The converter uses the Frame Sync line to synchronize when to run the conversion process and when to output data. If the Frame Sync pulses too fast, the converter will not behave as expected.

    FSYNC and SCLKs are provided by the microcontroller or DSP. I do not understand when you say out of phase. Out of phase with which line? The CLK or the SYNC. We explain in the data sheet that when using FSYNC and applying a SYNC, DOUT will go low while the digital filter is settling. This can take from 127 to 128 conversion periods. The reason that there is a 1 cycle difference between max and min is because if the SYNC line is pulsed during a conversion period, that conversion period needs to complete before the SYNC process can begin.

    Last question I am not sure what is being asked. You do not need to pulse the SYNC line as you free run the ADC. The SYNC line is only used for synchronization, generally done at the beginning following power on. Over time, I would imagine that the SCLK/FSYNC may slightly move out of phase with the master clock. The converter uses the Frame Sync input to time when new data is output so that it can be read efficiently.

    Regards,

    Tony Calabria

  • 0 in reply to Tony Calabria
    Intellectual 300 points

    Hello Tony,

        Thank you for the answers. It cleared all my questions.

    Best Regards,

    Calin