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ADS127L11: Jitter cleaner for external clock

reto hermann
Intellectual 720 points
Part Number: ADS127L11
Other Parts Discussed in Thread: LMK3C0105

Tool/software:

Hi
we intend to operate the ADS127L11 with an external clock. The external clock source frequency is adjustable within a range of some 100ppm. This feature is implemented by extending or reducing single clock cycle periods. In other words: The external clock source has a massive jitter of up tp +/-15 ns. To avoid degradation of the ADC performance, I'm thinking about using a PLL as a jitter cleaner. The project is very cost critical.

Do you have any suggestion which PLL device I could use? 

Or do you have another idea, than using a PLL for this problem?

Thank you for your reply!

BR
Reto

  • +1
    TI__Mastermind 46580 points

    Hello Reto,

    The ADS127L11 does not require an extremely low jitter clock, but +/-15ns is quite high and will degrade performance for any input signal frequency above 10Hz.  At 100kHz input, 10ps-rms jitter is the maximum recommended amount, but most clock oscillators can meet this requirement.

    Instead of trying to clean up this amount of jitter, something like the LMK3C0105 would definitely work.  It integrates a BAW oscillator, and the frequency can be adjusted using a fractional divider with 24b resolution over an I2C bus.

    Regards,
    Keith Nicholas
    Precision ADC Applications