• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 128 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DAC39RF12: DAC39RF12-EVM

DAC39RF12: DAC39RF12EVM, ADC12DJ5200SE and TSW14J59EVM - FPGA files for waveform generation and waveform Capture

Venu Reddy
Intellectual 320 points
Part Number: DAC39RF12
Other Parts Discussed in Thread: TSW14J59EVM

Tool/software:

Hi 

I recently purchased these units. I am interfacing them with FPGA eval board (TSW14J59EVM). Could you please share the vivado project files to load the data as well as the capturing the data for this. Do we need to procure a license for JESD204C to run the files?

Regards

Venu

  • 0
    Intellectual 320 points

    Any help on Vivado project files to setup the configuration, the following is the configuration I am interested in ..

                JESD204b/C 8b/10b
    JESD Configuration     DAC Analog parameters     Jmode 2
    Update rate 12G   Mxmode Des2XL or DES2XH   Lanes/stream 4
    Channel count 4 (2 IQ pairs)   DDS enabled 2   Lanecount 16
    Interpolation 6   DUC format Complex   LMFS 16-4-2-4
    Input data rate 2Gbps   Enable current doubler yes   LR 10Gbps
    Input BW 800MHz         Core clock 125MHz
    JESD Subclass  1         Serdes clock 125MHz
                Sysref K 64
                Sysref freq 7.8125MHz

  • 0 in reply to Venu Reddy
    TI__Expert 3440 points

    Veny,

    Please go the link below to request a JESD204C-IP from TI. 

    https://www.ti.com/drr/opn/TI204C-IP