DAC81401: Power Supply Sequencing

Hi Hansjurg,

This is not expected at all and for this device there is no power sequencing requirement. 

Before I can help here, please provide details mentioned below - 
1. Is this phenomenon happening on a single board or on multiple boards?
2. what is the power supply sequence when this high current phenomenon occurs?
3. Have you tried to check if you reduce the power supplies AVDD/ASS values?

Please do share the layout file if possible.

Thanks,
Sanjay

Dear Sanjay,

1.: We so far have only one prototype board with the aim of producing less than 10 PCBs (lab use at University)

2.: The first time we used a lab power supply with 3 outputs and an electronic enable switch which turns on all 3 (avdd=21.5V avss=-21.5V; iovdd=vdd=5V) used supplies at the same time. It could be that then the ground connection would have made an intermittand contact, at least this we assumed to be a possible cause. At this incident all five DAC's had failed.

The second time we used a home-build dual linear PS, made sure that at power-up it would not overshoot and level at +-21.5V. The +5V is taken subsequently from the +21.5V PS as shown in the schematic. Here the +-21.5V supplies ramp up in approx. 10 halfcycles of the mains (100ms), the +5V would be applied some 10's ms earlier. Since we use a digital isolator for the SPI bus signals, a condition can exist where the primary side of the isolator is unpowered and the secondary side has +5V from IOVDD and the SPI lines would default to 'High'.  This time only the first DAC in the daisy chain failed.

3.: During firmware development with the lab PS we used +-15V as AVDD and AVSS, which worked. But the final PCB will have to work with +-20V at the DAC output.

The layout files are attached.

The reason I enquired is the fact that the datasheet makes no reference to the AVSS regarding power sequencing. Since the next step would be to make a revision of the prototyp PCB we could easily implement changes if we are guided towards a 'better' way to apply the power. For example we could use a reduced voltage for IOVDD. I will make sure we use an isolator which defaults to 'LOW'.

Any more suggestions are welcome:)

Kind regards,

Hansjürgipa_daisy-chain_Kupfer TOP_GND_VCC_BOT.pdfipa_daisy-chain_Print.pdf

Hi Hansjurg,

Thanks for the details, this helps a lot. 

As per the design the device doesn't need any power sequencing and we have done a though power sequencing validation. I believe that, the high voltage power supplies must be overshooting. 

Here is my recommendation to make your design robust - 
1. Power on the AVDD/AVSS first >> next VDD >> next IOVDD and finally +5V_Dig isolator power supply.
2. You can add ferrite beads in the path of the power rails, will help in reducing the high frequency glitches. 

Rest of the things looks okay to me.

If possible, please probe the power supplies in a test condition where you are observing the high current issues. This is to establish if it's a genuine DAC81401 issue or not.

Thanks,
Sanjay