ADC12SJ1600: questions related to CLK_ALM

Noriyuki Takahashi

Part Number: ADC12SJ1600

Tool/software:

Hi team,

1. According to the description of CLK_ALM, the device monitor whether the internal clock dividers for the A and B channels do not match the C and D channels as below.

But, in case of ADC12SJ1600, the device has only channel A. So can this alarm function work in ADC12SJ1600?

2. According to the description of CLK_ALM, the device monitors internal clock dividers for the A and B channels do not match the C and D channels, while the datasheet mentions " The clocks in channel A are continuously compared to channel B. " according to 7.3.5.10.1 Clock Upset Detection as below. Could you explain this deifference?

3. The datasheet suggests how to enable the CLK_ALM in 7.3.5.10.1 Clock Upset Detection, however, they can't find PD_ACH and PD_BCH as the register bit. Could you tell what PD_ACH and PD_BCH are?

4. Can the function of CLK_ALM detect the unlock of C-PLL?

Regards,

Noriyuki Takahashi

3 months ago

0 Eric Kleckner 3 months ago

TI__Expert 6150 points

Hello Noriyuki,

The single channel variant does not support the CLK_ALM functionality only the dual and quad channel variants support this mode of operation as it requires there to be clocks from two ADCs at once. If they absolutely need the CLK_ALM they would need to look at using the dual or quad version and only using one channel.

Another recommendation for high reliability systems would be to run a continuous sysref to the ADC with the sysref processing sub system enabled and then if the ADC CLK is upset it will cause a realignment on the next sysref edge which in turn will cause the REALIGNED_ALM to fire.

Thanks,

Eric

0 Noriyuki Takahashi 3 months ago in reply to Eric Kleckner

TI__Genius 10980 points

Hi Eric,

Thanks.

Eric Kleckner said:
Another recommendation for high reliability systems would be to run a continuous sysref to the ADC with the sysref processing sub system enabled and then if the ADC CLK is upset it will cause a realignment on the next sysref edge which in turn will cause the REALIGNED_ALM to fire.

Could you give more explanation about "with the sysref processing sub system enabled"?

I am not sure what "the sysref processing sub system" mean.

Regards,

Noriyuki Takahshi

+1 Eric Kleckner 3 months ago in reply to Noriyuki Takahashi

TI__Expert 6150 points

Hi Noriyuki,

The device must be configured to receive a sysref by turning on the sysref receiver and sysref processing.

Thanks,

Eric

0 Noriyuki Takahashi 3 months ago in reply to Eric Kleckner

TI__Genius 10980 points

Hi Eric

Please let me ask one more question.

They understand that they need to confirm the register that is CPLL_LOCKED in order to confirm whether C-PLL is locked. However, are there anyways to confirm whether whether C-PLL is locked?

Regards,

Noriyuki Takahashi

0 Eric Kleckner 3 months ago in reply to Noriyuki Takahashi

TI__Expert 6150 points

Hi Noriyuki,

I am confused by your question the register bit will let them know if the CPLL is locked or not.

Thanks,

Eric

0 Noriyuki Takahashi 3 months ago in reply to Eric Kleckner

TI__Genius 10980 points

Eric,

Sorry for confusing. I jsut wanted to confirm CPLL_LOCKED is the only way to know if the CPLL is locked or not.

Regards,

Noriyuki Takahashii

0 Eric Kleckner 3 months ago in reply to Noriyuki Takahashi

TI__Expert 6150 points

Hi Noriyuki,

No problem, yes this is the only way to confirm the CPLL is locked.

Thanks,

Eric

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ADC12SJ1600: questions related to CLK_ALM