ADS9229: Configuration for 24-bit, DDR, without averaging, 1-lane output mode

Hello Shu, 

Welcome to TI's E2E Forum!  We are happy to hear that you are using ADS9229 in your project. 

To answer your questions:

Shu Wang said:

I'm trying to configure the ADS9229 to work in 24-bit, DDR, without averaging, 1-lane output mode. As Table 7-9 suggests, this configuration is possible

Regarding this, yes, 24-bit, DDR, 1-Lane, is possible, but it is only supported when averaging is enabled. Below Table 7-9, in the footnotes it notes that this mode is only supported when data averaging is enabled.  The "(2)" in those rows seems to be missing which I will note so it is updated on the datasheet. Thank you for bringing it to our attention. 

Shu Wang said:

Table 7-8 suggests the DATA_LANES should be set to 2 for my configuration. However, Figure 8-18 says this register should be set to 7, and all the CLK settings should be changed accordingly

Thank you for bringing this to our attention as well, we will make this change on our datasheets. the correct value for "DATA_LANES 0x12[2:0]" should be "7" on the rows that have "1" on the "Output Lanes" column. 

Regarding to the 240MHz you were seeing when configuring the device per Table 7-8, it would remain in 2-Lane mode and according to Table 7-9 and equation 4, this would make DCLK = 240MHz. if DATA_LANES,CLK1, CLK2, CLK3 & CLK5 are configured according to the descriptions in the register map then 480MHz should be attainable. 

That being said, we do recommend that if 24-bit, DDR, 1-Lane is used averaging should also enabled, since it is not supported without it.

The mode not being supported without averaging is also the reason why it is locked on the EVM GUI, to avoid configuring outside recommended modes. 

Best regards, 

Yolanda

Thanks, Yolanda Gonzalez.
FYI I am Shu Wang colleague, working on the same development.

We would appreciate your comments and clarifications on other inconsistencies of this ADS922x datasheet, namely:

• When comparing Table 7-8, lines 7 (or 5) with the register definition, an inconsistency is found in the parameters CLK1 and CLK3. Table 7-8 recommends CLK1,CLK3=0, while the register map says CLK1,CLK3 =1. If I understand your last reply correctly, the table configuration of the line 7 leads to setting DCLK=240M, while following the register-map configuration leads to DCLK=480M. I also understand that TI does not support 480M 1-lane DDR, but it could theoretically work.
• Tables 7-7 and 7-8. The use of INIT_1 here conflicts with the register definition on the figure. 8-11, as well as on the third line of table 7-11 (init sequence). Please confirm the correct use of INIT_1.
• In addition, INIT_1 column is empty, on table 7-8. Does it mean that it is a "don't care" on ADS9228 and ADS9229?
• ADC configuration change. This is not clearly addressed in the datasheet. Still, we understand that ADC configuration registers (such as data dormat and clock registers) can be changed in any order, and no action is required after a register change to apply the new configuration. Can you confirm this is correct? Or is there a recommended action to take prior to or after register changes?
• Power down mode. Paragraph 7.3.10 states "When the sampling clock is stopped, the ADC is in power-down and the output data, data clock, and frame clock are invalid.", and 7.4.2 states "The device registers are initialized to the default values after power-up.". Can you confirm that if the sampling clock is not applied anymore, the device will enter power down mode, and that, at wake-up, all configuration registers will be reset.

Thanks in advance for your help. Much appreciated!

Hello Simon, 

Apologies for the delay, I wanted to make sure on my end and with the internal team the correct configuration. Also, apologies for the confusion, since the configurations asked for were out of recommended in the datasheet I had to verify. 

I will answer your questions individually, but just as a summary/preface: Table 7-7 & Table 7-8 are correct. DATA_LANEs will always be 2, and only  DATA_RATE and CLK5 need to be configured depending on Data lanes or rates. 

There is an inconsistency between the register map and the tables in the datasheet, the datasheet was recently updated to include the final release of the higher speed versions of this family of devices, and this discrepancy was an oversight on our end. I have brought this up internally and we will update the datasheet to clarify and avoid this confusion again. My apologies for the confusion with my previous response. 

Simon D. said:

When comparing Table 7-8, lines 7 (or 5) with the register definition, an inconsistency is found in the parameters CLK1 and CLK3. Table 7-8 recommends CLK1,CLK3=0, while the register map says CLK1,CLK3 =1. If I understand your last reply correctly, the table configuration of the line 7 leads to setting DCLK=240M, while following the register-map configuration leads to DCLK=480M. I also understand that TI does not support 480M 1-lane DDR, but it could theoretically work.

Ideally yes, following the register map, Table 7-9, and leaving the OSR enable for the end, 480MHz should be attainable on the DCLK, but to ensure the best performance for this device, actual 480MHz on DCLK was not made available when in DDR mode.  For this I would suggest following Table 7-4 (assuming OSR 4) then setting CLK5 (Table 7-8) .

Simon D. said:

• Tables 7-7 and 7-8. The use of INIT_1 here conflicts with the register definition on the figure. 8-11, as well as on the third line of table 7-11 (init sequence). Please confirm the correct use of INIT_1.
• In addition, INIT_1 column is empty, on table 7-8. Does it mean that it is a "don't care" on ADS9228 and ADS9229?

Yes, since INIT_1 is only needed for ADS9227, this will remain default for ADS9229 or "don't care"

Simon D. said:

ADC configuration change. This is not clearly addressed in the datasheet. Still, we understand that ADC configuration registers (such as data dormat and clock registers) can be changed in any order, and no action is required after a register change to apply the new configuration. Can you confirm this is correct? Or is there a recommended action to take prior to or after register changes?

aside the initialization sequence for ADS9229 after power up, enabling SPI read and setting the respective register bank when writing to the device, no special configuration needed before or after the register changes. 

Simon D. said:

Power down mode. Paragraph 7.3.10 states "When the sampling clock is stopped, the ADC is in power-down and the output data, data clock, and frame clock are invalid.", and 7.4.2 states "The device registers are initialized to the default values after power-up.". Can you confirm that if the sampling clock is not applied anymore, the device will enter power down mode, and that, at wake-up, all configuration registers will be reset.

When there is no sampling clock the device does go into power down mode, as does setting the PWDN pin low or setting the PD registers accordingly. 

For register configurations resetting to default, this happens after power-up or after reset (RESET pin or reset register). I would recommend resetting if there is a need to return the device to default settings. 

Best regards, 

Yolanda

Dear Yolanda,

Thanks for your reply. We have successfully made the chip work at 24-bit, DDR, without averaging, in 2-lane output mode. However, we observed some strange behaviors in the output. When the ADC input is floating, our FPGA data deserializer generates outputs as shown in the figure below. Note that the data has been converted to the real values in Volt. Compared to the 10V max input range, the noise level seems too high, and the data distributed in a banded manner also looks very strange to me.

As a comparison, we also tried to run the ADC at 24-bit, DDR, with an average of 2. As shown below, we don't see the strange band-distributed data anymore, and the noise level is around 5mV max, which makes sense to us.

And it is also worth mentioning that during the whole operation, we wrote some fixed patterns in the user_bit register and we are always checking the received user bits in our FPGA, so we are pretty sure that our data decoder is not causing this issue. After some investigation, I noticed another conflict in your datasheet. In the Table 7-12, the register 0x34[1] should be written a 0x1 (which means a 0x0002 should be written to 0x34 to my understanding). However, the Figure 8-37 indicates the bit 3-0 are reserved and shouldn't be changed. Instead, the bit 4 LAT_EN should be set to 1 (which means a 0x0010 should be written to 0x34 to my understanding).

I tried to write 0x0002 to 0x34 in my setup, and surprisingly, it solved the issue. As shown below, I observed a noise of ~10mV, which makes sense to me.

Based on these results, my understanding is, the contents in Figure 8-37 are wrong. 0x0002 should be written to the address 0x34 for optimum INL performance, as indicated in Table 7-12. Please confirm if my understanding is correct, and if not, please let me know the correct configuration and the possible reason for the issue I had.

Thanks in advance for your prompt reply.

Hello Shu, 

You are correct, Figure 8-37 is incorrect, I will make sure to note this internally to ensure it gets updated in the next datasheet revision. Thank you for bringing this to our attention. We really appreciate your detailed description and process. 

We will make sure to update Figure 8-36, 35, 12 to show the correct bit placement of "LAT_EN" accordingly. Please follow the instructions on Table 7-12 for the time being. 

If I could ask, do you happen to have an attenuation stage in the signal chain to allow the 10V input range? The ADS9229 FSR is ±3.2V, with the absolute input voltage of the AIN pins and Vcm±1.6V

Best regards, 

Yolanda