Hi,
I am using my own fpga development board (Terasic DE4) interfacing with DAC5682zEVM.
My EVM has been configured with transform output. I found that the output amplitude is acting weird for the same digital data transmitted to the DAC in a repeated pattern.
For example I did two tests:
1. Given a circular repeated pattern of {40000,30000,20000,10000,0,0,10000,20000,30000,40000}. The output of DAC on the scope is not a symmetric pattern in a period in respect to the center. The sample of '10000' before '0' has a lower amplitude than the sample of '10000' after the '0'. same for other samples with the same digital value, they always have different analogue output amplitudes even if they have the same digital inputs. My sampling rate is 100MHz. PLL bypassed, single channel, no interpolation.
2. Given a repeated pattern of increasing DAC input of 16'h4000 starting from 0, the saw-shaped pattern amplitude level is not evenly distributed. therefore I am thinking the conversion is kind of non-linear in my case.
Is this expected or is there anything I could be doing incorrectly with the setup? or could it because of the transformer output? I am confused... My application needs a precisely defined amplitude-wise analogue signal therefore I am quite worried about what I have seen here. Do you have any suggestions?
Best wishes,
Liang
